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42d4d3baac
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
/*
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* Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/generic_delay_timer.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#pragma weak bl2_el3_early_platform_setup
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#pragma weak bl2_el3_plat_arch_setup
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#pragma weak bl2_el3_plat_prepare_exit
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#define MAP_BL2_EL3_TOTAL MAP_REGION_FLAT( \
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bl2_el3_tzram_layout.total_base, \
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bl2_el3_tzram_layout.total_size, \
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MT_MEMORY | MT_RW | MT_SECURE)
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static meminfo_t bl2_el3_tzram_layout;
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/*
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* Perform arm specific early platform setup. At this moment we only initialize
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* the console and the memory layout.
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*/
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void arm_bl2_el3_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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arm_console_boot_init();
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/*
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* Allow BL2 to see the whole Trusted RAM. This is determined
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* statically since we cannot rely on BL1 passing this information
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* in the RESET_TO_BL2 case.
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*/
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bl2_el3_tzram_layout.total_base = ARM_BL_RAM_BASE;
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bl2_el3_tzram_layout.total_size = ARM_BL_RAM_SIZE;
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/* Initialise the IO layer and register platform IO devices */
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plat_arm_io_setup();
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}
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void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
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u_register_t arg1 __unused,
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u_register_t arg2 __unused,
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u_register_t arg3 __unused)
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{
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arm_bl2_el3_early_platform_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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plat_arm_interconnect_init();
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/*
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* Enable Interconnect coherency for the primary CPU's cluster.
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*/
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plat_arm_interconnect_enter_coherency();
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generic_delay_timer_init();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only initializes the mmu in a quick and dirty way.
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******************************************************************************/
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void arm_bl2_el3_plat_arch_setup(void)
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{
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#if USE_COHERENT_MEM
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/* Ensure ARM platforms dont use coherent memory
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* in RESET_TO_BL2
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*/
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assert(BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE == 0U);
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#endif
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const mmap_region_t bl_regions[] = {
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MAP_BL2_EL3_TOTAL,
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ARM_MAP_BL_RO,
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{0}
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};
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setup_page_tables(bl_regions, plat_arm_get_mmap());
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#ifdef __aarch64__
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enable_mmu_el3(0);
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#else
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enable_mmu_svc_mon(0);
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#endif
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}
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void bl2_el3_plat_arch_setup(void)
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{
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arm_bl2_el3_plat_arch_setup();
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}
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void bl2_el3_plat_prepare_exit(void)
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{
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}
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