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arm-trusted-firmware/lib/cpus/aarch64
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Arvind Ram Prakash 42d4d3baac refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 
BL2_AT_EL3 is an overloaded macro which has two uses:
	1. When BL2 is entry point into TF-A(no BL1)
	2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2023-03-15 11:43:14 +00:00
..
a64fx.S feat(cpus): add a64fx cpu to tf-a 2022-07-07 07:17:25 +09:00
aem_generic.S FVP_Base_AEMv8A platform: Fix cache maintenance operations 2019-08-16 11:30:37 +00:00
cortex_a35.S Cortex-A35: Implement workaround for errata 855472 2019-04-17 13:46:43 +01:00
cortex_a53.S lib/cpus: Report AT speculative erratum workaround 2020-08-18 10:49:27 +01:00
cortex_a55.S feat(plat/qti): fix to support cpu errata 2022-07-29 18:15:32 +05:30
cortex_a57.S fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00
cortex_a65.S Introducing support for Cortex-A65 2019-10-02 18:12:28 +02:00
cortex_a65ae.S Introducing support for Cortex-A65AE 2019-10-03 15:38:31 +02:00
cortex_a72.S fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00
cortex_a73.S fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00
cortex_a75.S fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00
cortex_a75_pubsub.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
cortex_a76.S fix(cpus): workaround for Cortex-A76 erratum 2743102 2022-11-03 14:50:58 -05:00
cortex_a76ae.S fix(security): workaround for CVE-2022-23960 for A76AE, A78AE, A78C 2022-03-21 08:57:09 -05:00
cortex_a77.S fix(cpus): workaround for Cortex-A77 erratum 2743100 2022-11-10 15:51:16 +00:00
cortex_a78.S fix(cpus): workaround for Cortex-A78 erratum 2742426 2023-03-08 14:58:05 -06:00
cortex_a78_ae.S fix(errata): workaround for Cortex A78 AE erratum 2395408 2022-03-24 10:55:48 +00:00
cortex_a78c.S fix(cpus): workaround for Cortex-A78C erratum 2779484 2023-03-08 22:00:14 +01:00
cortex_a510.S fix(cpus): workaround for Cortex-A510 erratum 2684597 2023-01-25 09:40:33 +00:00
cortex_a710.S fix(cpus): workaround for Cortex-A710 erratum 2282622 2023-01-09 23:17:48 -06:00
cortex_a715.S refactor(cpu): update IP names of Makalu CPU lib 2022-08-31 18:31:29 +01:00
cortex_hayes.S feat(cpu): add support for Hayes CPU 2021-09-30 19:30:39 +02:00
cortex_hunter.S fix(security): workaround for CVE-2022-23960 2022-05-11 19:05:48 +02:00
cortex_hunter_elp_arm.S feat(cpu): add library support for Hunter ELP 2022-10-07 12:44:04 +01:00
cortex_x1.S fix(security): workaround for CVE-2022-23960 for Cortex-X1 2022-05-11 15:24:37 +02:00
cortex_x2.S fix(cpus): workaround for Cortex-X2 erratum 2282622 2023-01-11 11:34:19 -06:00
cortex_x3.S fix(cpus): workaround for Cortex-X3 erratum 2615812 2022-11-17 09:41:40 +00:00
cpu_helpers.S refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 2023-03-15 11:43:14 +00:00
cpuamu.c Sanitise includes across codebase 2019-01-04 10:43:17 +00:00
cpuamu_helpers.S Add support for Branch Target Identification 2019-05-24 14:44:45 +01:00
denver.S fix(cpus/denver): use CPU_NO_EXTRA3_FUNC for all variants 2022-05-24 15:32:33 +01:00
dsu_helpers.S fix(errata): workaround for DSU-110 erratum 2313941 2022-05-11 19:05:36 +02:00
generic.S arm_fpga: Add support for unknown MPIDs 2020-09-25 15:45:50 +01:00
neoverse_e1.S DSU: Apply erratum 936184 for Neoverse N1/E1 2019-06-11 14:01:32 +01:00
neoverse_n1.S fix(cpus): workaround for Neoverse N1 erratum 2743102 2022-11-03 14:47:04 -05:00
neoverse_n1_pubsub.c Rename Cortex-Ares to Neoverse N1 2019-02-19 13:50:07 +00:00
neoverse_n2.S fix(cpus): workaround for Neoverse N2 erratum 2743089 2022-12-21 16:35:39 +01:00
neoverse_n_common.S Add support for Neoverse-N2 CPUs. 2020-11-30 19:12:56 +00:00
neoverse_poseidon.S fix(security): workaround for CVE-2022-23960 2022-05-11 19:05:48 +02:00
neoverse_v1.S fix(cpus): workaround for Neoverse V1 errata 2779461 2023-01-19 12:14:39 -06:00
neoverse_v2.S refactor(cpu): use the updated IP name for Demeter CPU 2022-10-03 15:31:40 +05:30
qemu_max.S Add support for QEMU "max" CPU 2021-04-13 12:31:40 +01:00
rainier.S fix(errata): workaround for Rainier erratum 1868343 2022-01-05 17:16:19 +00:00
runtime_errata.S fix(cpus): workaround for Cortex-A510 erratum 2684597 2023-01-25 09:40:33 +00:00
wa_cve_2017_5715_bpiall.S fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00
wa_cve_2017_5715_mmu.S fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 2022-03-18 01:01:34 +02:00
wa_cve_2022_23960_bhb.S fix(security): optimisations for CVE-2022-23960 2022-10-26 16:45:12 -05:00
wa_cve_2022_23960_bhb_vector.S fix(security): workaround for CVE-2022-23960 2022-03-10 23:57:14 -06:00