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42d4d3baac
BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
265 lines
6.3 KiB
ArmAsm
265 lines
6.3 KiB
ArmAsm
/*
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* Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#include <common/bl_common.h>
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#include <lib/el3_runtime/cpu_data.h>
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#if defined(IMAGE_BL1) || defined(IMAGE_BL32) || \
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(defined(IMAGE_BL2) && RESET_TO_BL2)
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/*
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* The reset handler common to all platforms. After a matching
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* cpu_ops structure entry is found, the correponding reset_handler
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* in the cpu_ops is invoked. The reset handler is invoked very early
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* in the boot sequence and it is assumed that we can clobber r0 - r10
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* without the need to follow AAPCS.
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* Clobbers: r0 - r10
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*/
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.globl reset_handler
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func reset_handler
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mov r8, lr
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/* The plat_reset_handler can clobber r0 - r7 */
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bl plat_reset_handler
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/* Get the matching cpu_ops pointer (clobbers: r0 - r5) */
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bl get_cpu_ops_ptr
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops reset handler */
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ldr r1, [r0, #CPU_RESET_FUNC]
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cmp r1, #0
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mov lr, r8
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bxne r1
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bx lr
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endfunc reset_handler
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#endif
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#ifdef IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
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/*
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* void prepare_cpu_pwr_dwn(unsigned int power_level)
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*
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* Prepare CPU power down function for all platforms. The function takes
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* a domain level to be powered down as its parameter. After the cpu_ops
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* pointer is retrieved from cpu_data, the handler for requested power
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* level is called.
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*/
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.globl prepare_cpu_pwr_dwn
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func prepare_cpu_pwr_dwn
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/*
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* If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
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* power down handler for the last power level
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*/
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mov r2, #(CPU_MAX_PWR_DWN_OPS - 1)
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cmp r0, r2
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movhi r0, r2
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push {r0, lr}
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bl _cpu_data
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pop {r2, lr}
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ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the appropriate power down handler */
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mov r1, #CPU_PWR_DWN_OPS
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add r1, r1, r2, lsl #2
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ldr r1, [r0, r1]
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#if ENABLE_ASSERTIONS
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cmp r1, #0
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ASM_ASSERT(ne)
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#endif
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bx r1
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endfunc prepare_cpu_pwr_dwn
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/*
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* Initializes the cpu_ops_ptr if not already initialized
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* in cpu_data. This must only be called after the data cache
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* is enabled. AAPCS is followed.
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*/
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.globl init_cpu_ops
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func init_cpu_ops
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push {r4 - r6, lr}
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bl _cpu_data
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mov r6, r0
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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cmp r1, #0
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bne 1f
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bl get_cpu_ops_ptr
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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str r0, [r6, #CPU_DATA_CPU_OPS_PTR]!
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1:
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pop {r4 - r6, pc}
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endfunc init_cpu_ops
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#endif /* IMAGE_BL32 */
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/*
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* The below function returns the cpu_ops structure matching the
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* midr of the core. It reads the MIDR and finds the matching
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* entry in cpu_ops entries. Only the implementation and part number
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* are used to match the entries.
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* Return :
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* r0 - The matching cpu_ops pointer on Success
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* r0 - 0 on failure.
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* Clobbers: r0 - r5
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*/
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.globl get_cpu_ops_ptr
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func get_cpu_ops_ptr
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/* Get the cpu_ops start and end locations */
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ldr r4, =(__CPU_OPS_START__ + CPU_MIDR)
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ldr r5, =(__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov r0, #0
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/* Read the MIDR_EL1 */
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ldcopr r2, MIDR
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ldr r3, =CPU_IMPL_PN_MASK
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/* Retain only the implementation and part number using mask */
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and r2, r2, r3
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1:
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/* Check if we have reached end of list */
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cmp r4, r5
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bhs error_exit
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/* load the midr from the cpu_ops */
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ldr r1, [r4], #CPU_OPS_SIZE
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and r1, r1, r3
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/* Check if midr matches to midr of this core */
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cmp r1, r2
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bne 1b
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/* Subtract the increment and offset to get the cpu-ops pointer */
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sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR)
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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error_exit:
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bx lr
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endfunc get_cpu_ops_ptr
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/*
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* Extract CPU revision and variant, and combine them into a single numeric for
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* easier comparison.
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*/
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.globl cpu_get_rev_var
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func cpu_get_rev_var
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ldcopr r1, MIDR
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/*
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* Extract the variant[23:20] and revision[3:0] from r1 and pack it in
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* r0[0:7] as variant[7:4] and revision[3:0]:
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*
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* First extract r1[23:16] to r0[7:0] and zero fill the rest. Then
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* extract r1[3:0] into r0[3:0] retaining other bits.
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*/
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ubfx r0, r1, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS)
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bfi r0, r1, #MIDR_REV_SHIFT, #MIDR_REV_BITS
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bx lr
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endfunc cpu_get_rev_var
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/*
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* Compare the CPU's revision-variant (r0) with a given value (r1), for errata
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* application purposes. If the revision-variant is less than or same as a given
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* value, indicates that errata applies; otherwise not.
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*/
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.globl cpu_rev_var_ls
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func cpu_rev_var_ls
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cmp r0, r1
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movls r0, #ERRATA_APPLIES
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movhi r0, #ERRATA_NOT_APPLIES
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bx lr
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endfunc cpu_rev_var_ls
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/*
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* Compare the CPU's revision-variant (r0) with a given value (r1), for errata
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* application purposes. If the revision-variant is higher than or same as a
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* given value, indicates that errata applies; otherwise not.
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*/
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.globl cpu_rev_var_hs
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func cpu_rev_var_hs
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cmp r0, r1
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movge r0, #ERRATA_APPLIES
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movlt r0, #ERRATA_NOT_APPLIES
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bx lr
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endfunc cpu_rev_var_hs
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#if REPORT_ERRATA
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/*
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* void print_errata_status(void);
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*
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* Function to print errata status for CPUs of its class. Must be called only:
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*
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* - with MMU and data caches are enabled;
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* - after cpu_ops have been initialized in per-CPU data.
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*/
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.globl print_errata_status
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func print_errata_status
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/* r12 is pushed only for the sake of 8-byte stack alignment */
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push {r4, r5, r12, lr}
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#ifdef IMAGE_BL1
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/*
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* BL1 doesn't have per-CPU data. So retrieve the CPU operations
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* directly.
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*/
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bl get_cpu_ops_ptr
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ldr r0, [r0, #CPU_ERRATA_FUNC]
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cmp r0, #0
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blxne r0
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#else
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/*
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* Retrieve pointer to cpu_ops, and further, the errata printing
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* function. If it's non-NULL, jump to the function in turn.
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*/
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bl _cpu_data
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#if ENABLE_ASSERTIONS
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cmp r0, #0
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ASM_ASSERT(ne)
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#endif
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ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
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#if ENABLE_ASSERTIONS
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cmp r1, #0
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ASM_ASSERT(ne)
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#endif
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ldr r0, [r1, #CPU_ERRATA_FUNC]
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cmp r0, #0
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beq 1f
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mov r4, r0
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/*
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* Load pointers to errata lock and printed flag. Call
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* errata_needs_reporting to check whether this CPU needs to report
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* errata status pertaining to its class.
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*/
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ldr r0, [r1, #CPU_ERRATA_LOCK]
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ldr r1, [r1, #CPU_ERRATA_PRINTED]
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bl errata_needs_reporting
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cmp r0, #0
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blxne r4
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1:
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#endif
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pop {r4, r5, r12, pc}
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endfunc print_errata_status
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#endif
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