Arvind Ram Prakash 42d4d3baac refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3 ... BL2_AT_EL3 is an overloaded macro which has two uses: 1. When BL2 is entry point into TF-A(no BL1) 2. When BL2 is running at EL3 exception level These two scenarios are not exactly same even though first implicitly means second to be true. To distinguish between these two use cases we introduce new macros. BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2. Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where BL2 runs at EL3 (including four world systems). BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the repository. Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72 Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>		2023-03-15 11:43:14 +00:00
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aem_generic.S	Make errata reporting mandatory for CPU files	2018-10-29 09:54:32 +00:00
cortex_a5.S	Make errata reporting mandatory for CPU files	2018-10-29 09:54:32 +00:00
cortex_a7.S	Make errata reporting mandatory for CPU files	2018-10-29 09:54:32 +00:00
cortex_a9.S	Cortex A9:errata 794073 workaround	2019-04-12 10:10:32 +00:00
cortex_a12.S	Make errata reporting mandatory for CPU files	2018-10-29 09:54:32 +00:00
cortex_a15.S	fix(security): update Cortex-A15 CPU lib files for CVE-2022-23960	2022-04-28 20:33:09 +02:00
cortex_a17.S	Cortex-A17: Implement workaround for errata 852423	2019-03-13 15:40:45 +00:00
cortex_a32.S	Make errata reporting mandatory for CPU files	2018-10-29 09:54:32 +00:00
cortex_a53.S	Cortex-A53: Workarounds for 819472, 824069 and 827319	2019-02-28 09:56:58 +00:00
cortex_a57.S	fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72	2022-05-05 18:38:38 +02:00
cortex_a72.S	fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72	2022-05-05 18:38:38 +02:00
cpu_helpers.S	refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3	2023-03-15 11:43:14 +00:00