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https://github.com/ARM-software/arm-trusted-firmware.git
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fbc415d204
This corrects the MISRA violation C2012-10.4: Both operands of an operator in which the usual arithmetic conversions are performed shall have the same essential type category. The condition is explicitly checked against 0U, appending 'U' and typecasting for unsigned comparison. Change-Id: Ia352e3cf261b52777c1c431701e1e6c3be9cd279 Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
144 lines
3.2 KiB
C
144 lines
3.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Macros IDs for AMD Versal Gen 2
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*
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* Copyright (c) 2023-2024, Advanced Micro Devices, Inc. All rights reserved.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#ifndef _VERSAL2_SCMI_H
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#define _VERSAL2_SCMI_H
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#define CLK_GEM0_0 0U
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#define CLK_GEM0_1 1U
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#define CLK_GEM0_2 2U
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#define CLK_GEM0_3 3U
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#define CLK_GEM0_4 4U
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#define CLK_GEM1_0 5U
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#define CLK_GEM1_1 6U
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#define CLK_GEM1_2 7U
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#define CLK_GEM1_3 8U
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#define CLK_GEM1_4 9U
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#define CLK_SERIAL0_0 10U
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#define CLK_SERIAL0_1 11U
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#define CLK_SERIAL1_0 12U
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#define CLK_SERIAL1_1 13U
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#define CLK_UFS0_0 14U
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#define CLK_UFS0_1 15U
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#define CLK_UFS0_2 16U
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#define CLK_USB0_0 17U
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#define CLK_USB0_1 18U
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#define CLK_USB0_2 19U
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#define CLK_USB1_0 20U
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#define CLK_USB1_1 21U
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#define CLK_USB1_2 22U
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#define CLK_MMC0_0 23U
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#define CLK_MMC0_1 24U
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#define CLK_MMC0_2 25U
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#define CLK_MMC1_0 26U
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#define CLK_MMC1_1 27U
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#define CLK_MMC1_2 28U
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#define CLK_TTC0_0 29U
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#define CLK_TTC1_0 30U
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#define CLK_TTC2_0 31U
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#define CLK_TTC3_0 32U
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#define CLK_TTC4_0 33U
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#define CLK_TTC5_0 34U
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#define CLK_TTC6_0 35U
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#define CLK_TTC7_0 36U
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#define CLK_I2C0_0 37U
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#define CLK_I2C1_0 38U
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#define CLK_I2C2_0 39U
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#define CLK_I2C3_0 40U
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#define CLK_I2C4_0 41U
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#define CLK_I2C5_0 42U
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#define CLK_I2C6_0 43U
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#define CLK_I2C7_0 44U
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#define CLK_OSPI0_0 45U
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#define CLK_QSPI0_0 46U
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#define CLK_QSPI0_1 47U
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#define CLK_WWDT0_0 48U
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#define CLK_WWDT1_0 49U
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#define CLK_WWDT2_0 50U
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#define CLK_WWDT3_0 51U
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#define CLK_ADMA0_0 52U
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#define CLK_ADMA0_1 53U
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#define CLK_ADMA1_0 54U
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#define CLK_ADMA1_1 55U
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#define CLK_ADMA2_0 56U
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#define CLK_ADMA2_1 57U
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#define CLK_ADMA3_0 58U
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#define CLK_ADMA3_1 59U
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#define CLK_ADMA4_0 60U
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#define CLK_ADMA4_1 61U
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#define CLK_ADMA5_0 62U
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#define CLK_ADMA5_1 63U
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#define CLK_ADMA6_0 64U
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#define CLK_ADMA6_1 65U
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#define CLK_ADMA7_0 66U
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#define CLK_ADMA7_1 67U
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#define CLK_CAN0_0 68U
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#define CLK_CAN0_1 69U
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#define CLK_CAN1_0 70U
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#define CLK_CAN1_1 71U
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#define CLK_CAN2_0 72U
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#define CLK_CAN2_1 73U
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#define CLK_CAN3_0 74U
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#define CLK_CAN3_1 75U
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#define CLK_PS_GPIO_0 76U
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#define CLK_PMC_GPIO_0 77U
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#define CLK_SPI0_0 78U
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#define CLK_SPI0_1 79U
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#define CLK_SPI1_0 80U
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#define CLK_SPI1_1 81U
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#define CLK_I3C0_0 82U
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#define CLK_I3C1_0 83U
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#define CLK_I3C2_0 84U
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#define CLK_I3C3_0 85U
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#define CLK_I3C4_0 86U
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#define CLK_I3C5_0 87U
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#define CLK_I3C6_0 88U
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#define CLK_I3C7_0 89U
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#define RESET_GEM0_0 0
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#define RESET_GEM1_0 1
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#define RESET_SERIAL0_0 2
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#define RESET_SERIAL1_0 3
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#define RESET_UFS0_0 4
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#define RESET_I2C0_0 5
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#define RESET_I2C1_0 6
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#define RESET_I2C2_0 7
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#define RESET_I2C3_0 8
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#define RESET_I2C4_0 9
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#define RESET_I2C5_0 10
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#define RESET_I2C6_0 11
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#define RESET_I2C7_0 12
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#define RESET_I2C8_0 13
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#define RESET_OSPI0_0 14
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#define RESET_USB0_0 15
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#define RESET_USB0_1 16
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#define RESET_USB0_2 17
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#define RESET_USB1_0 18
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#define RESET_USB1_1 19
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#define RESET_USB1_2 20
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#define RESET_MMC0_0 21
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#define RESET_MMC1_0 22
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#define RESET_SPI0_0 23
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#define RESET_SPI1_0 24
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#define RESET_QSPI0_0 25
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#define RESET_I3C0_0 26
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#define RESET_I3C1_0 27
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#define RESET_I3C2_0 28
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#define RESET_I3C3_0 29
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#define RESET_I3C4_0 30
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#define RESET_I3C5_0 31
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#define RESET_I3C6_0 32
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#define RESET_I3C7_0 33
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#define RESET_I3C8_0 34
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#define RESET_UFSPHY_0 35
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#define PD_USB0 0
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#define PD_USB1 1
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#endif /* _VERSAL2_SCMI_H */
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