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5f32fd2145
Neoverse V3 erratum 2970647 that applies to r0p0 and is fixed in r0p1. In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize which register to return when reading the value of MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively. The workaround is to do an ISB prior to an MRS read to either MPIDR_EL1 and MIDR_EL1. SDEN documentation: https://developer.arm.com/documentation/SDEN-2891958/latest/ Change-Id: Iedf7d799451f0be58a5da1f93f7f5b6940f2bb35 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
131 lines
4.1 KiB
ArmAsm
131 lines
4.1 KiB
ArmAsm
/*
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* Copyright (c) 2022-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_neoverse_v3_3701767
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add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767, NO_APPLY_AT_RESET
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check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2)
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workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647
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/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
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ldr x0, =0x1
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msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
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ldr x0, =0xd5380000
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msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
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ldr x0, =0xFFFFFF40
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msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
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ldr x0, =0x000080010033f
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msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
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isb
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workaround_reset_end neoverse_v3, ERRATUM(2970647)
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check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0)
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start neoverse_v3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set NEOVERSE_V3_CPUECTLR_EL1, BIT(46)
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workaround_reset_end neoverse_v3, CVE(2024, 5660)
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check_erratum_ls neoverse_v3, CVE(2024, 5660), CPU_REV(0, 1)
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workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse V3 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_v3
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_v3, CVE(2022,23960)
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check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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workaround_reset_start neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set NEOVERSE_V3_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end neoverse_v3, CVE(2024, 7881)
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check_erratum_chosen neoverse_v3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_v3_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
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NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc neoverse_v3_core_pwr_dwn
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cpu_reset_func_start neoverse_v3
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end neoverse_v3
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/* ---------------------------------------------
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* This function provides Neoverse V3 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v3_regs, "aS"
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neoverse_v3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v3_cpu_reg_dump
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adr x6, neoverse_v3_regs
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mrs x8, NEOVERSE_V3_CPUECTLR_EL1
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ret
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endfunc neoverse_v3_cpu_reg_dump
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declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
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neoverse_v3_reset_func, \
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neoverse_v3_core_pwr_dwn
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declare_cpu_ops_wa_4 neoverse_v3, NEOVERSE_V3_MIDR, \
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neoverse_v3_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_neoverse_v3_7881, \
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neoverse_v3_core_pwr_dwn
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