Djam/arm-trusted-firmware
1
0
Fork 0
mirror of https://github.com/ARM-software/arm-trusted-firmware.git synced 2025-04-08 05:43:53 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

fix(cpus): workaround for Neoverse-V3 erratum 2970647

Browse source 
Neoverse V3 erratum 2970647 that applies to r0p0 and is fixed in r0p1.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.

The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-2891958/latest/

Change-Id: Iedf7d799451f0be58a5da1f93f7f5b6940f2bb35
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
This commit is contained in:
Govindraj Raja 2025-02-07 14:31:39 -06:00
parent 09c1edb84b
commit 5f32fd2145
3 changed files with 22 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
docs/design/cpu-specific-build-macros.rst
View file

@ -580,6 +580,9 @@ For Neoverse V2, the following errata build flags are defined :
For Neoverse V3, the following errata build flags are defined :
- ``ERRATA_V3_2970647``: This applies errata 2970647 workaround to Neoverse-V3
CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
- ``ERRATA_V3_3701767``: This applies errata 3701767 workaround to Neoverse-V3
CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2 of the CPU and
is still open.

15
lib/cpus/aarch64/neoverse_v3.S
View file

@ -28,6 +28,21 @@ add_erratum_entry neoverse_v3, ERRATUM(3701767), ERRATA_V3_3701767, NO_APPLY_AT_
check_erratum_ls neoverse_v3, ERRATUM(3701767), CPU_REV(0, 2)
workaround_reset_start neoverse_v3, ERRATUM(2970647), ERRATA_V3_2970647
/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
ldr x0, =0x1
msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
ldr x0, =0xd5380000
msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
ldr x0, =0xFFFFFF40
msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
ldr x0, =0x000080010033f
msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
isb
workaround_reset_end neoverse_v3, ERRATUM(2970647)
check_erratum_ls neoverse_v3, ERRATUM(2970647), CPU_REV(0, 0)
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
#endif /* WORKAROUND_CVE_2022_23960 */

4
lib/cpus/cpu-ops.mk
View file

@ -564,6 +564,10 @@ CPU_FLAG_LIST += ERRATA_V1_2743233
# still open.
CPU_FLAG_LIST += ERRATA_V1_2779461
# Flag to apply erratum 2970647 workaround during reset. This erratum applies
# to revisions r0p0 of the Neoverse V3 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_V3_2970647
# Flag to apply erratum 3701767 workaround during context save/restore of
# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1 and r0p2 of
# the Neoverse V3 cpu and is still open.