Jit Loon Lim 2d46b2e461 feat(intel): increase bl2 size limit ... There are several features included in BL2 causing the size getting bigger for RELEASE mode. When build with DEBUG mode, the size will be bigger thus causing BL2 image has exceeded its limits. Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>		2023-11-03 23:39:48 +08:00
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agilex_clock_manager.h	fix(intel): fix Agilex and N5X clock manager to main PLL C0	2023-04-14 09:19:31 +08:00
agilex_memory_controller.h	feat(intel): restructure sys mgr for Agilex	2023-05-23 21:13:05 +08:00
agilex_mmc.h	plat: intel: set DRVSEL and SMPLSEL for DWMMC	2020-06-08 22:03:34 +00:00
agilex_pinmux.h	feat(intel): setup FPGA interface for Agilex	2022-11-22 23:35:36 +08:00
agilex_system_manager.h	feat(intel): restructure sys mgr for Agilex	2023-05-23 21:13:05 +08:00
socfpga_plat_def.h	feat(intel): increase bl2 size limit	2023-11-03 23:39:48 +08:00