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27a8bcdc37
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame.
At this point the binary output of all errata was checked with the
script from commit 19136. The reported discrepancies are immaterial.
All errata have been checked that they get invoked.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ideb6397f4ac7c3c1d04549a57af43bfa7ef25c1d
167 lines
5.3 KiB
ArmAsm
167 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78_ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
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/* Set bit 8 in ECTLR_EL1 */
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mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
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bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
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msr CORTEX_A78_AE_CPUECTLR_EL1, x0
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workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
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check_erratum_range cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 0), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
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msr S3_6_c15_c8_0, xzr
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ldr x0, =0x10E3900002
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #1
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800082
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF00083
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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mov x0, #2
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10E3800200
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FFF003E0
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
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check_erratum_range cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 0), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
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/* -------------------------------------------------------
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* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
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* behave like PLD/PRFM LD and not cause invalidations to
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* other PE caches. There might be a small performance
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* degradation to this workaround for certain workloads
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* that share data.
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_A78_AE_ACTLR2_EL1
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orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
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msr CORTEX_A78_AE_ACTLR2_EL1, x0
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workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
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check_erratum_range cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 0), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
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/* --------------------------------------------------------
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* Disable folding of demand requests into older prefetches
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* with L2 miss requests outstanding by setting the
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* CPUACTLR2_EL1[40] to 1.
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* --------------------------------------------------------
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*/
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mrs x0, CORTEX_A78_AE_ACTLR2_EL1
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orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
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msr CORTEX_A78_AE_ACTLR2_EL1, x0
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workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
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check_erratum_range cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 0), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A78AE generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a78_ae
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
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check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_a78_ae
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el3, x0
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/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
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msr actlr_el2, x0
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/* Enable group0 counters */
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mov x0, #CORTEX_A78_AMU_GROUP0_MASK
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msr CPUAMCNTENSET0_EL0, x0
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/* Enable group1 counters */
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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cpu_reset_func_end cortex_a78_ae
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/* -------------------------------------------------------
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* HW will do the cache maintenance while powering down
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* -------------------------------------------------------
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*/
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func cortex_a78_ae_core_pwr_dwn
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/* -------------------------------------------------------
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* Enable CPU power down bit in power control register
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* -------------------------------------------------------
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*/
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mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a78_ae_core_pwr_dwn
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errata_report_shim cortex_a78_ae
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/* -------------------------------------------------------
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* This function provides cortex_a78_ae specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* -------------------------------------------------------
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*/
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.section .rodata.cortex_a78_ae_regs, "aS"
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cortex_a78_ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78_ae_cpu_reg_dump
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adr x6, cortex_a78_ae_regs
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mrs x8, CORTEX_A78_CPUECTLR_EL1
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ret
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endfunc cortex_a78_ae_cpu_reg_dump
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declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
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cortex_a78_ae_reset_func, \
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cortex_a78_ae_core_pwr_dwn
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