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https://github.com/ARM-software/arm-trusted-firmware.git
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refactor(cpus): convert the Cortex-A78AE to use the errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround and checking
sequences remain unchanged and preserve their git blame.
At this point the binary output of all errata was checked with the
script from commit 19136. The reported discrepancies are immaterial.
All errata have been checked that they get invoked.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ideb6397f4ac7c3c1d04549a57af43bfa7ef25c1d
This commit is contained in:
Boyan Karatotev
Sona Mathew
parent
aff3fa210b
commit
27a8bcdc37
1 changed files with 25 additions and 170 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2022, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
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* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -22,50 +22,16 @@
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 1941500.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_1941500_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_1941500
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cbz x0, 1f
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workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
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/* Set bit 8 in ECTLR_EL1 */
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mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
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bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
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msr CORTEX_A78_AE_CPUECTLR_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_1941500_wa
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workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
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func check_errata_1941500
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_1941500
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 1951502.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_1951502_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_1951502
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cbz x0, 1f
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check_erratum_range cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 0), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
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msr S3_6_c15_c8_0, xzr
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ldr x0, =0x10E3900002
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msr S3_6_c15_c8_2, x0
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@ -91,33 +57,11 @@ func errata_a78_ae_1951502_wa
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x2001003FF
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msr S3_6_c15_c8_1, x0
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workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
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isb
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1:
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ret x17
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endfunc errata_a78_ae_1951502_wa
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func check_errata_1951502
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_1951502
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 2376748.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_2376748_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_2376748
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cbz x0, 1f
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check_erratum_range cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 0), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
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/* -------------------------------------------------------
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* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
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* behave like PLD/PRFM LD and not cause invalidations to
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@ -129,32 +73,11 @@ func errata_a78_ae_2376748_wa
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mrs x0, CORTEX_A78_AE_ACTLR2_EL1
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orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
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msr CORTEX_A78_AE_ACTLR2_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_2376748_wa
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workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
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func check_errata_2376748
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_2376748
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/* --------------------------------------------------
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* Errata Workaround for A78 AE Erratum 2395408.
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* This applies to revisions r0p0 and r0p1 of A78 AE.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a78_ae_2395408_wa
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/* Compare x0 against revisions r0p0 - r0p1 */
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mov x17, x30
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bl check_errata_2395408
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cbz x0, 1f
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check_erratum_range cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 0), CPU_REV(0, 1)
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workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
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/* --------------------------------------------------------
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* Disable folding of demand requests into older prefetches
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* with L2 miss requests outstanding by setting the
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@ -164,56 +87,23 @@ func errata_a78_ae_2395408_wa
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mrs x0, CORTEX_A78_AE_ACTLR2_EL1
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orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
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msr CORTEX_A78_AE_ACTLR2_EL1, x0
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isb
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1:
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ret x17
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endfunc errata_a78_ae_2395408_wa
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workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
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func check_errata_2395408
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/* Applies to revisions r0p0 and r0p1. */
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mov x1, #CPU_REV(0, 0)
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mov x2, #CPU_REV(0, 1)
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b cpu_rev_var_range
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endfunc check_errata_2395408
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check_erratum_range cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 0), CPU_REV(0, 1)
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78-AE
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* -------------------------------------------------
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workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A78AE generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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func cortex_a78_ae_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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override_vector_table wa_cve_vbar_cortex_a78_ae
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
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#if ERRATA_A78_AE_1941500
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mov x0, x18
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bl errata_a78_ae_1941500_wa
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#endif
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#if ERRATA_A78_AE_1951502
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mov x0, x18
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bl errata_a78_ae_1951502_wa
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#endif
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#if ERRATA_A78_AE_2376748
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mov x0, x18
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bl errata_a78_ae_2376748_wa
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#endif
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#if ERRATA_A78_AE_2395408
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mov x0, x18
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bl errata_a78_ae_2395408_wa
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#endif
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check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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cpu_reset_func_start cortex_a78_ae
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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@ -233,19 +123,7 @@ func cortex_a78_ae_reset_func
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mov x0, #CORTEX_A78_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A78AE generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a78_ae
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret x19
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endfunc cortex_a78_ae_reset_func
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cpu_reset_func_end cortex_a78_ae
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/* -------------------------------------------------------
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* HW will do the cache maintenance while powering down
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@ -263,30 +141,7 @@ func cortex_a78_ae_core_pwr_dwn
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ret
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endfunc cortex_a78_ae_core_pwr_dwn
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/*
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* Errata printing function for cortex_a78_ae. Must follow AAPCS.
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*/
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#if REPORT_ERRATA
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func cortex_a78_ae_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
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report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
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report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
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report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a78_ae_errata_report
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#endif
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errata_report_shim cortex_a78_ae
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/* -------------------------------------------------------
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* This function provides cortex_a78_ae specific
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