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2590e819eb
MPMM is a core-specific microarchitectural feature. It has been present in every Arm core since the Cortex-A510 and has been implemented in exactly the same way. Despite that, it is enabled more like an architectural feature with a top level enable flag. This utilised the identical implementation. This duality has left MPMM in an awkward place, where its enablement should be generic, like an architectural feature, but since it is not, it should also be core-specific if it ever changes. One choice to do this has been through the device tree. This has worked just fine so far, however, recent implementations expose a weakness in that this is rather slow - the device tree has to be read, there's a long call stack of functions with many branches, and system registers are read. In the hot path of PSCI CPU powerdown, this has a significant and measurable impact. Besides it being a rather large amount of code that is difficult to understand. Since MPMM is a microarchitectural feature, its correct placement is in the reset function. The essence of the current enablement is to write CPUPPMCR_EL3.MPMM_EN if CPUPPMCR_EL3.MPMMPINCTL == 0. Replacing the C enablement with an assembly macro in each CPU's reset function achieves the same effect with just a single close branch and a grand total of 6 instructions (versus the old 2 branches and 32 instructions). Having done this, the device tree entry becomes redundant. Should a core that doesn't support MPMM arise, this can cleanly be handled in the reset function. As such, the whole ENABLE_MPMM_FCONF and platform hooks mechanisms become obsolete and are removed. Change-Id: I1d0475b21a1625bb3519f513ba109284f973ffdf Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
125 lines
4 KiB
ArmAsm
125 lines
4 KiB
ArmAsm
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a720.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue cortex_a720
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.global check_erratum_cortex_a720_3699561
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132
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sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26)
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workaround_reset_end cortex_a720, ERRATUM(2792132)
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check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1)
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workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092
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sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11)
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workaround_reset_end cortex_a720, ERRATUM(2844092)
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check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1)
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workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
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/* Erratum 2926083 workaround is required only if SPE is enabled */
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#if ENABLE_SPE_FOR_NS != 0
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/* Check if Static profiling extension is implemented or present. */
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mrs x1, id_aa64dfr0_el1
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ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
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cbz x0, 1f
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/* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
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sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57)
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sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58)
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1:
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#endif
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workaround_reset_end cortex_a720, ERRATUM(2926083)
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check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1)
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workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794
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sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37)
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workaround_reset_end cortex_a720, ERRATUM(2940794)
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check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1)
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workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex A720 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_a720
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a720, CVE(2022, 23960)
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check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561
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check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2)
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cpu_reset_func_start cortex_a720
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/* Disable speculative loads */
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msr SSBS, xzr
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enable_mpmm
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cpu_reset_func_end cortex_a720
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a720_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_a720_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex A720-specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a720_regs, "aS"
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cortex_a720_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a720_cpu_reg_dump
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adr x6, cortex_a720_regs
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mrs x8, CORTEX_A720_CPUECTLR_EL1
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ret
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endfunc cortex_a720_cpu_reg_dump
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declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \
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cortex_a720_reset_func, \
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cortex_a720_core_pwr_dwn
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