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742ca2307f
This change makes AMU auxiliary counters configurable on a per-core
basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`.
Auxiliary counters can be described via the `HW_CONFIG` device tree if
the `ENABLE_AMU_FCONF` build option is enabled, or the platform must
otherwise implement the `plat_amu_topology` function.
A new phandle property for `cpu` nodes (`amu`) has been introduced to
the `HW_CONFIG` specification to allow CPUs to describe the view of
their own AMU:
```
cpu0: cpu@0 {
...
amu = <&cpu0_amu>;
};
```
Multiple cores may share an `amu` handle if they implement the
same set of auxiliary counters.
AMU counters are described for one or more AMUs through the use of a new
`amus` node:
```
amus {
cpu0_amu: amu-0 {
#address-cells = <1>;
#size-cells = <0>;
counter@0 {
reg = <0>;
enable-at-el3;
};
counter@n {
reg = <n>;
...
};
};
};
```
This structure describes the **auxiliary** (group 1) AMU counters.
Architected counters have architecturally-defined behaviour, and as
such do not require DTB entries.
These `counter` nodes support two properties:
- The `reg` property represents the counter register index.
- The presence of the `enable-at-el3` property determines whether
the firmware should enable the counter prior to exiting EL3.
Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28
Signed-off-by: Chris Kay <chris.kay@arm.com>
142 lines
4.9 KiB
ReStructuredText
142 lines
4.9 KiB
ReStructuredText
Activity Monitor Unit (AMU) Bindings
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====================================
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To support platform-defined Activity Monitor Unit (|AMU|) auxiliary counters
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through FCONF, the ``HW_CONFIG`` device tree accepts several |AMU|-specific
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nodes and properties.
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Bindings
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^^^^^^^^
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.. contents::
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:local:
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``/cpus/cpus/cpu*`` node properties
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"""""""""""""""""""""""""""""""""""
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The ``cpu`` node has been augmented to support a handle to an associated |AMU|
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view, which should describe the counters offered by the core.
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+---------------+-------+---------------+-------------------------------------+
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| Property name | Usage | Value type | Description |
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+===============+=======+===============+=====================================+
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| ``amu`` | O | ``<phandle>`` | If present, indicates that an |AMU| |
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| | | | is available and its counters are |
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| | | | described by the node provided. |
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+---------------+-------+---------------+-------------------------------------+
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``/cpus/amus`` node properties
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""""""""""""""""""""""""""""""
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The ``amus`` node describes the |AMUs| implemented by the cores in the system.
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This node does not have any properties.
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``/cpus/amus/amu*`` node properties
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"""""""""""""""""""""""""""""""""""
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An ``amu`` node describes the layout and meaning of the auxiliary counter
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registers of one or more |AMUs|, and may be shared by multiple cores.
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+--------------------+-------+------------+------------------------------------+
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| Property name | Usage | Value type | Description |
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+====================+=======+============+====================================+
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| ``#address-cells`` | R | ``<u32>`` | Value shall be 1. Specifies that |
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| | | | the ``reg`` property array of |
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| | | | children of this node uses a |
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| | | | single cell. |
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+--------------------+-------+------------+------------------------------------+
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| ``#size-cells`` | R | ``<u32>`` | Value shall be 0. Specifies that |
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| | | | no size is required in the ``reg`` |
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| | | | property in children of this node. |
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+--------------------+-------+------------+------------------------------------+
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``/cpus/amus/amu*/counter*`` node properties
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""""""""""""""""""""""""""""""""""""""""""""
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A ``counter`` node describes an auxiliary counter belonging to the parent |AMU|
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view.
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+-------------------+-------+-------------+------------------------------------+
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| Property name | Usage | Value type | Description |
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+===================+=======+=============+====================================+
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| ``reg`` | R | array | Represents the counter register |
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| | | | index, and must be a single cell. |
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+-------------------+-------+-------------+------------------------------------+
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| ``enable-at-el3`` | O | ``<empty>`` | The presence of this property |
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| | | | indicates that this counter should |
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| | | | be enabled prior to EL3 exit. |
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+-------------------+-------+-------------+------------------------------------+
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Example
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^^^^^^^
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An example system offering four cores made up of two clusters, where the cores
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of each cluster share different |AMUs|, may use something like the following:
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.. code-block::
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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amus {
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amu0: amu-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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counterX: counter@0 {
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reg = <0>;
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enable-at-el3;
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};
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counterY: counter@1 {
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reg = <1>;
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enable-at-el3;
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};
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};
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amu1: amu-1 {
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#address-cells = <1>;
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#size-cells = <0>;
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counterZ: counter@0 {
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reg = <0>;
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enable-at-el3;
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};
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};
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};
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cpu0@00000 {
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...
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amu = <&amu0>;
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};
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cpu1@00100 {
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...
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amu = <&amu0>;
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};
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cpu2@10000 {
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...
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amu = <&amu1>;
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};
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cpu3@10100 {
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...
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amu = <&amu1>;
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};
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}
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In this situation, ``cpu0`` and ``cpu1`` (the two cores in the first cluster),
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share the view of their AMUs defined by ``amu0``. Likewise, ``cpu2`` and
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``cpu3`` (the two cores in the second cluster), share the view of their |AMUs|
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defined by ``amu1``. This will cause ``counterX`` and ``counterY`` to be enabled
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for both ``cpu0`` and ``cpu1``, and ``counterZ`` to be enabled for both ``cpu2``
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and ``cpu3``.
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