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c5c160cddd
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an (optional) integrated L2 cache that might need to be flushed if the whole cluster is powered down. However, unlike Cortex-A53 there is currently no L2 cache flush in the cluster_pwr_dwn implementation for some reason. This causes problems if there is unwritten data left in the L2 cache during a cluster power off. Fix this by adding the L2 cache flush similar to cortex_a53.S. Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
81 lines
1.4 KiB
ArmAsm
81 lines
1.4 KiB
ArmAsm
/*
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* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a7.h>
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#include <cpu_macros.S>
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a7_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A7_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a7_disable_smp
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func cortex_a7_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A7_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a7_enable_smp
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func cortex_a7_reset_func
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b cortex_a7_enable_smp
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endfunc cortex_a7_reset_func
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func cortex_a7_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a7_disable_smp
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endfunc cortex_a7_core_pwr_dwn
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func cortex_a7_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Flush L2 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a7_disable_smp
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endfunc cortex_a7_cluster_pwr_dwn
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errata_report_shim cortex_a7
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declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
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cortex_a7_reset_func, \
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cortex_a7_core_pwr_dwn, \
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cortex_a7_cluster_pwr_dwn
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