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https://github.com/ARM-software/arm-trusted-firmware.git
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21a01dac87
1. Update emif rsthdshk macro 2. Update mailbox return status 3. Update bridge return status Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
177 lines
7.2 KiB
C
177 lines
7.2 KiB
C
/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGX_MEMORYCONTROLLER_H
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#define AGX_MEMORYCONTROLLER_H
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#define AGX_MPFE_IOHMC_REG_DRAMADDRW 0xf80100a8
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#define AGX_MPFE_IOHMC_CTRLCFG0 0xf8010028
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#define AGX_MPFE_IOHMC_CTRLCFG1 0xf801002c
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#define AGX_MPFE_IOHMC_CTRLCFG2 0xf8010030
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#define AGX_MPFE_IOHMC_CTRLCFG3 0xf8010034
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#define AGX_MPFE_IOHMC_DRAMADDRW 0xf80100a8
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#define AGX_MPFE_IOHMC_DRAMTIMING0 0xf8010050
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#define AGX_MPFE_IOHMC_CALTIMING0 0xf801007c
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#define AGX_MPFE_IOHMC_CALTIMING1 0xf8010080
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#define AGX_MPFE_IOHMC_CALTIMING2 0xf8010084
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#define AGX_MPFE_IOHMC_CALTIMING3 0xf8010088
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#define AGX_MPFE_IOHMC_CALTIMING4 0xf801008c
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#define AGX_MPFE_IOHMC_CALTIMING9 0xf80100a0
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#define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0)
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#define AGX_MPFE_IOHMC_CTRLCFG1_CFG_ADDR_ORDER(value) \
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(((value) & 0x00000060) >> 5)
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#define AGX_MPFE_HMC_ADP_ECCCTRL1 0xf8011100
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#define AGX_MPFE_HMC_ADP_ECCCTRL2 0xf8011104
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#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT 0xf8011218
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#define AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE 0x0000000f
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#define AGX_MPFE_HMC_ADP_RSTHANDSHAKECTRL 0xf8011214
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#define AGX_MPFE_IOHMC_REG_CTRLCFG1 0xf801002c
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#define AGX_MPFE_IOHMC_REG_NIOSRESERVE0_OFST 0xf8010110
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#define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0)
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#define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5)
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#define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16)
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#define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14)
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#define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10)
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#define AGX_MPFE_DDR(x) (0xf8000000 + x)
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#define AGX_MPFE_HMC_ADP_DDRCALSTAT 0xf801100c
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#define AGX_MPFE_DDR_MAIN_SCHED 0xf8000400
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#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF 0xf8000408
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#define AGX_MPFE_DDR_MAIN_SCHED_DDRTIMING 0xf800040c
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#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET_MSK 0x0000001f
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#define AGX_MPFE_DDR_MAIN_SCHED_DDRMODE 0xf8000410
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#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV 0xf800043c
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#define AGX_MPFE_DDR_MAIN_SCHED_READLATENCY 0xf8000414
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#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE 0xf8000438
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#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAWBANK_OFST 10
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#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_FAW_OFST 4
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#define AGX_MPFE_DDR_MAIN_SCHED_ACTIVATE_RRD_OFST 0
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#define AGX_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f)
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#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_OFST 0
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#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTORD_MSK (BIT(0) | BIT(1))
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#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_OFST 2
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#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSRDTOWR_MSK (BIT(2) | BIT(3))
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#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_OFST 4
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#define AGX_MPFE_DDR_MAIN_SCHED_DEVTODEV_BUSWRTORD_MSK (BIT(4) | BIT(5))
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#define AGX_MPFE_HMC_ADP(x) (0xf8011000 + (x))
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#define AGX_MPFE_HMC_ADP_HPSINTFCSEL 0xf8011210
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#define AGX_MPFE_HMC_ADP_DDRIOCTRL 0xf8011008
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#define HMC_ADP_DDRIOCTRL 0x8
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#define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0)
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#define HMC_ADP_DDRIOCTRL_CTRL_BURST_LENGTH(x) (((x) & 0x00003e00) >> 9)
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#define ADP_DRAMADDRWIDTH 0xe0
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#define ACT_TO_ACT_DIFF_BANK(value) (((value) & 0x00fc0000) >> 18)
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#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
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#define ACT_TO_RDWR(value) (((value) & 0x0000003f) >> 0)
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#define ACT_TO_ACT(value) (((value) & 0x0003f000) >> 12)
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/* timing 2 */
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#define RD_TO_RD_DIFF_CHIP(value) (((value) & 0x00000fc0) >> 6)
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#define RD_TO_WR_DIFF_CHIP(value) (((value) & 0x3f000000) >> 24)
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#define RD_TO_WR(value) (((value) & 0x00fc0000) >> 18)
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#define RD_TO_PCH(value) (((value) & 0x00000fc0) >> 6)
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/* timing 3 */
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#define CALTIMING3_WR_TO_RD_DIFF_CHIP(value) (((value) & 0x0003f000) >> 12)
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#define CALTIMING3_WR_TO_RD(value) (((value) & 0x00000fc0) >> 6)
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/* timing 4 */
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#define PCH_TO_VALID(value) (((value) & 0x00000fc0) >> 6)
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#define DDRTIMING_BWRATIO_OFST 31
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#define DDRTIMING_WRTORD_OFST 26
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#define DDRTIMING_RDTOWR_OFST 21
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#define DDRTIMING_BURSTLEN_OFST 18
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#define DDRTIMING_WRTOMISS_OFST 12
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#define DDRTIMING_RDTOMISS_OFST 6
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#define DDRTIMING_ACTTOACT_OFST 0
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#define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x3) >> 0)
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#define DDRMODE_AUTOPRECHARGE_OFST 1
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#define DDRMODE_BWRATIOEXTENDED_OFST 0
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#define AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x7f) >> 0)
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#define AGX_MPFE_IOHMC_REG_CTRLCFG0_CFG_MEM_TYPE(x) (((x) & 0x0f) >> 0)
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#define AGX_CCU_CPU0_MPRT_DDR 0xf7004400
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#define AGX_CCU_CPU0_MPRT_MEM0 0xf70045c0
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#define AGX_CCU_CPU0_MPRT_MEM1A 0xf70045e0
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#define AGX_CCU_CPU0_MPRT_MEM1B 0xf7004600
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#define AGX_CCU_CPU0_MPRT_MEM1C 0xf7004620
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#define AGX_CCU_CPU0_MPRT_MEM1D 0xf7004640
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#define AGX_CCU_CPU0_MPRT_MEM1E 0xf7004660
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#define AGX_CCU_IOM_MPRT_MEM0 0xf7018560
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#define AGX_CCU_IOM_MPRT_MEM1A 0xf7018580
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#define AGX_CCU_IOM_MPRT_MEM1B 0xf70185a0
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#define AGX_CCU_IOM_MPRT_MEM1C 0xf70185c0
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#define AGX_CCU_IOM_MPRT_MEM1D 0xf70185e0
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#define AGX_CCU_IOM_MPRT_MEM1E 0xf7018600
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#define AGX_NOC_FW_DDR_SCR 0xf8020200
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#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0xf802021c
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#define AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT 0xf8020218
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#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0xf802029c
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#define AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0xf8020298
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#define AGX_SOC_NOC_FW_DDR_SCR_ENABLE 0xf8020200
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#define AGX_SOC_NOC_FW_DDR_SCR_ENABLESET 0xf8020204
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#define AGX_CCU_NOC_DI_SET_MSK 0x10
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#define AGX_SYSMGR_CORE_HMC_CLK 0xffd120b4
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#define AGX_SYSMGR_CORE_HMC_CLK_STATUS 0x00000001
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#define AGX_MPFE_IOHMC_NIOSRESERVE0_NIOS_RESERVE0(x) (((x) & 0xffff) >> 0)
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#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_MSK 0x00000003
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#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE_OFST 0
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#define AGX_MPFE_HMC_ADP_HPSINTFCSEL_ENABLE 0x001f1f1f
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#define AGX_IOHMC_CTRLCFG1_ENABLE_ECC_OFST 7
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#define AGX_MPFE_HMC_ADP_ECCCTRL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
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#define AGX_MPFE_HMC_ADP_ECCCTRL1_CNT_RST_SET_MSK 0x00000100
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#define AGX_MPFE_HMC_ADP_ECCCTRL1_ECC_EN_SET_MSK 0x00000001
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#define AGX_MPFE_HMC_ADP_ECCCTRL2_AUTOWB_EN_SET_MSK 0x00000001
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#define AGX_MPFE_HMC_ADP_ECCCTRL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
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#define AGX_MPFE_HMC_ADP_ECCCTRL2_RMW_EN_SET_MSK 0x00000100
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#define AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(value) (((value) & 0x1) >> 0)
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#define AGX_MPFE_HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00003) >> 0)
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#define IOHMC_DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) (((x) & 0x03c00) >> 10)
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#define IOHMC_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH(x) (((x) & 0x0c000) >> 14)
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#define IOHMC_DRAMADDRW_CFG_COL_ADDR_WIDTH(x) (((x) & 0x0001f) >> 0)
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#define IOHMC_DRAMADDRW_CFG_CS_ADDR_WIDTH(x) (((x) & 0x70000) >> 16)
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#define IOHMC_DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) (((x) & 0x003e0) >> 5)
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#define AGX_SDRAM_0_LB_ADDR 0x0
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#define AGX_DDR_SIZE 0x40000000
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/* Macros */
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#define SOCFPGA_MEMCTRL_ECCCTRL1 0x008
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#define SOCFPGA_MEMCTRL_ERRINTEN 0x010
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#define SOCFPGA_MEMCTRL_ERRINTENS 0x014
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#define SOCFPGA_MEMCTRL_ERRINTENR 0x018
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#define SOCFPGA_MEMCTRL_INTMODE 0x01C
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#define SOCFPGA_MEMCTRL_INTSTAT 0x020
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#define SOCFPGA_MEMCTRL_DIAGINTTEST 0x024
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#define SOCFPGA_MEMCTRL_DERRADDRA 0x02C
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#define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \
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+ (SOCFPGA_MEMCTRL_##_reg))
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int init_hard_memory_controller(void);
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#endif
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