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1f1c0206d8
SIMICS builds have different UART configurations compared to hardware build. Hence, this patch defines a macro to differentiate between both. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Change-Id: Iadecd5445e06611486ac3c6a214a6d0dc8ccd27b
50 lines
1.5 KiB
Makefile
50 lines
1.5 KiB
Makefile
#
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# Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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PLAT_INCLUDES := \
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-Iplat/intel/soc/n5x/include/ \
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-Iplat/intel/soc/common/drivers/ \
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-Iplat/intel/soc/common/include/
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# Include GICv2 driver files
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include drivers/arm/gic/v2/gicv2.mk
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DM_GICv2_SOURCES := \
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${GICV2_SOURCES} \
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plat/common/plat_gicv2.c
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PLAT_BL_COMMON_SOURCES := \
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${DM_GICv2_SOURCES} \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/ti/uart/aarch64/16550_console.S \
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lib/xlat_tables/aarch64/xlat_tables.c \
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lib/xlat_tables/xlat_tables_common.c \
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plat/intel/soc/common/aarch64/platform_common.c \
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plat/intel/soc/common/aarch64/plat_helpers.S \
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plat/intel/soc/common/socfpga_delay_timer.c
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BL2_SOURCES +=
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BL31_SOURCES += \
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drivers/arm/cci/cci.c \
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lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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plat/common/plat_psci_common.c \
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plat/intel/soc/n5x/bl31_plat_setup.c \
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plat/intel/soc/common/socfpga_psci.c \
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plat/intel/soc/common/socfpga_sip_svc.c \
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plat/intel/soc/common/socfpga_topology.c \
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plat/intel/soc/common/sip/socfpga_sip_fcs.c \
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plat/intel/soc/common/soc/socfpga_mailbox.c \
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plat/intel/soc/common/soc/socfpga_reset_manager.c
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PROGRAMMABLE_RESET_ADDRESS := 0
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BL2_AT_EL3 := 1
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BL2_INV_DCACHE := 0
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MULTI_CONSOLE_API := 1
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SIMICS_BUILD := 0
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USE_COHERENT_MEM := 1
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