Boyan Karatotev 1d6d6802dd fix(pmu): unconditionally save PMCR_EL0 ... Reading back a RES0 bit does not necessarily mean it will be read as 0. The Arm ARM explicitly warns against doing this. The PMU initialisation code tries to set such bits to 1 (in MDCR_EL3) regardless of whether they are in use or are RES0, checking their value could be wrong and PMCR_EL0 might not end up being saved. Save PMCR_EL0 unconditionally to prevent this. Remove the security state change as the outgoing state is not relevant to what the root world context should look like. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: Id43667d37b0e2da3ded0beaf23fa0d4f9013f470		2023-05-05 13:16:18 +01:00
..
aarch64	fix(pmu): unconditionally save PMCR_EL0	2023-05-05 13:16:18 +01:00
bl31.ld.S	fix(fvp): work around BL31 progbits exceeded	2023-04-03 17:53:05 +01:00
bl31.mk	refactor(cm): make SVE and SME build dependencies logical	2023-05-05 13:16:18 +01:00
bl31_context_mgmt.c	feat(rme): add context management changes for FEAT_RME	2021-10-05 18:41:35 +02:00
bl31_main.c	refactor(context-mgmt): move FEAT_HCX save/restore into C	2023-01-11 16:02:58 +00:00
bl31_traps.c	feat(el3-runtime): handle traps for IMPDEF registers accesses	2023-04-30 11:04:59 +01:00
ehf.c	fix(bl31): allow use of EHF with S-EL2 SPMC	2022-08-30 08:29:25 -07:00
interrupt_mgmt.c	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00