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refactor(cm): make SVE and SME build dependencies logical
Currently, enabling SME forces SVE off. However, the SME enablement requires SVE to be enabled, which is reflected in code. This is the opposite of what the build flags require. Further, the few platforms that enable SME also explicitly enable SVE. Their platform.mk runs after the defaults.mk file so this override never materializes. As a result, the override is only present on the commandline. Change it to something sensible where if SME is on then code can rely on SVE being on too. Do this with a check in the Makefile as it is the more widely used pattern. This maintains all valid use cases but subtly changes corner cases no one uses at the moment to require a slightly different combination of flags. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: If7ca3972ebc3c321e554533d7bc81af49c2472be
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parent
c194aa0c6c
commit
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6 changed files with 42 additions and 47 deletions
9
Makefile
9
Makefile
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@ -912,11 +912,20 @@ ifeq (${ENABLE_RME},1)
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endif
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endif
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ifneq (${ENABLE_SME_FOR_NS},0)
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ifeq (${ENABLE_SVE_FOR_NS},0)
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$(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS")
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endif
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endif
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# Secure SME/SVE requires the non-secure component as well
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ifeq (${ENABLE_SME_FOR_SWD},1)
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ifeq (${ENABLE_SME_FOR_NS},0)
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$(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS")
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endif
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ifeq (${ENABLE_SVE_FOR_SWD},0)
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$(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD")
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endif
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endif
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ifeq (${ENABLE_SVE_FOR_SWD},1)
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ifeq (${ENABLE_SVE_FOR_NS},0)
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@ -101,12 +101,10 @@ endif
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ifneq (${ENABLE_SME_FOR_NS},0)
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BL31_SOURCES += lib/extensions/sme/sme.c
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BL31_SOURCES += lib/extensions/sve/sve.c
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else
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endif
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ifneq (${ENABLE_SVE_FOR_NS},0)
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BL31_SOURCES += lib/extensions/sve/sve.c
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endif
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endif
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ifneq (${ENABLE_MPAM_FOR_LOWER_ELS},0)
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BL31_SOURCES += lib/extensions/mpam/mpam.c
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@ -436,7 +436,8 @@ Common build options
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(SME), SVE, and FPU/SIMD for the non-secure world only. These features share
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registers so are enabled together. Using this option without
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ENABLE_SME_FOR_SWD=1 will cause SME, SVE, and FPU/SIMD instructions in secure
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world to trap to EL3. SME is an optional architectural feature for AArch64
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world to trap to EL3. Requires ``ENABLE_SVE_FOR_NS`` to be set as SME is a
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superset of SVE. SME is an optional architectural feature for AArch64
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and TF-A support is experimental. At this time, this build option cannot be
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used on systems that have SPD=spmd/SPM_MM or ENABLE_RME, and attempting to
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build with these options will fail. This flag can take the values 0 to 2, to
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@ -450,10 +451,9 @@ Common build options
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align with the ``FEATURE_DETECTION`` mechanism. Default is 0.
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- ``ENABLE_SME_FOR_SWD``: Boolean option to enable the Scalable Matrix
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Extension for secure world use along with SVE and FPU/SIMD, ENABLE_SME_FOR_NS
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must also be set to use this. If enabling this, the secure world MUST
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handle context switching for SME, SVE, and FPU/SIMD registers to ensure that
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no data is leaked to non-secure world. This is experimental. Default is 0.
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Extension for secure world. Used along with SVE and FPU/SIMD.
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ENABLE_SME_FOR_NS and ENABLE_SVE_FOR_SWD must also be set to use this.
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This is experimental. Default is 0.
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- ``ENABLE_SPE_FOR_NS`` : Numeric value to enable Statistical Profiling
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extensions. This is an optional architectural feature for AArch64.
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@ -469,17 +469,15 @@ Common build options
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This is to avoid corruption of the Non-secure world data in the Z-registers
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which are aliased by the SIMD and FP registers. The build option is not
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compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
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assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS`` enabled.
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This flag can take the values 0 to 2, to align with the ``FEATURE_DETECTION``
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mechanism. The default is 2 but is automatically disabled when
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ENABLE_SME_FOR_NS is enabled ( set to 1 or 2) since SME encompasses SVE.
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At this time, this build option cannot be used on systems that have SPM_MM
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enabled.
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assert on platforms where SVE is implemented and ``ENABLE_SVE_FOR_NS``
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enabled. This flag can take the values 0 to 2, to align with the
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``FEATURE_DETECTION`` mechanism. At this time, this build option cannot be
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used on systems that have SPM_MM enabled. The default is 1.
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- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
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SVE is an optional architectural feature for AArch64. Note that this option
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requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it
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is automatically disabled when the target architecture is AArch32.
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requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
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automatically disabled when the target architecture is AArch32.
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- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
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checks in GCC. Allowed values are "all", "strong", "default" and "none". The
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@ -517,12 +517,13 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
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amu_enable(el2_unused, ctx);
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}
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/* Enable SME, SVE, and FPU/SIMD for non-secure world. */
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/* Enable SVE and FPU/SIMD */
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if (is_feat_sve_supported()) {
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sve_enable(ctx);
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}
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if (is_feat_sme_supported()) {
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sme_enable(ctx);
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} else if (is_feat_sve_supported()) {
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/* Enable SVE and FPU/SIMD for non-secure world. */
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sve_enable(ctx);
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}
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if (is_feat_mpam_supported()) {
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@ -553,22 +554,7 @@ static void manage_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
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static void manage_extensions_secure(cpu_context_t *ctx)
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{
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#if IMAGE_BL31
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if (is_feat_sme_supported()) {
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if (ENABLE_SME_FOR_SWD) {
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/*
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* Enable SME, SVE, FPU/SIMD in secure context, secure manager
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* must ensure SME, SVE, and FPU/SIMD context properly managed.
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*/
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sme_enable(ctx);
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} else {
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/*
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* Disable SME, SVE, FPU/SIMD in secure context so non-secure
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* world can safely use the associated registers.
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*/
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sme_disable(ctx);
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}
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} else if (is_feat_sve_supported()) {
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if (is_feat_sve_supported()) {
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if (ENABLE_SVE_FOR_SWD) {
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/*
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* Enable SVE and FPU in secure context, secure manager must
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@ -585,6 +571,21 @@ static void manage_extensions_secure(cpu_context_t *ctx)
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}
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}
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if (is_feat_sme_supported()) {
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if (ENABLE_SME_FOR_SWD) {
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/*
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* Enable SME, SVE, FPU/SIMD in secure context, secure manager
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* must ensure SME, SVE, and FPU/SIMD context properly managed.
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*/
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sme_enable(ctx);
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} else {
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/*
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* Disable SME, SVE, FPU/SIMD in secure context so non-secure
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* world can safely use the associated registers.
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*/
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sme_disable(ctx);
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}
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}
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#endif /* IMAGE_BL31 */
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}
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@ -65,9 +65,6 @@ void sme_enable(cpu_context_t *context)
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/* Reset CPTR_EL3 value. */
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write_cptr_el3(cptr_el3);
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isb();
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/* Enable SVE/FPU in addition to SME. */
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sve_enable(context);
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}
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void sme_disable(cpu_context_t *context)
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@ -401,14 +401,6 @@ SVE_VECTOR_LEN := 2048
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# SME defaults to disabled
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ENABLE_SME_FOR_NS := 0
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ENABLE_SME_FOR_SWD := 0
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# If SME is enabled then force SVE off
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ifneq (${ENABLE_SME_FOR_NS},0)
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override ENABLE_SVE_FOR_NS := 0
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override ENABLE_SVE_FOR_SWD := 0
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endif
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# SME2 defaults to disabled
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ENABLE_SME2_FOR_NS := 0
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SANITIZE_UB := off
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