Sona Mathew 15a04615bb fix(cpus): workaround for Cortex-A715 erratum 2413290 ... Cortex-A715 erratum 2413290 is a Cat B erratum that is present only in revision r1p0 and is fixed in r1p1. The errata is only present when SPE(Statistical Profiling Extension) is enabled. The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11 when SPE is enabled, ENABLE_SPE_FOR_NS=1. SDEN documentation: https://developer.arm.com/documentation/SDEN2148827/latest Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>		2024-03-11 10:48:10 -05:00
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a5ds	refactor(bl2): make post image handling platform-specific	2023-10-30 10:29:03 +00:00
arm_fpga	build(fpga): correctly handle gcc as linker for LTO	2024-02-24 00:59:06 +03:00
common	fix(rotpk): move rotpk definitions out of arm_def.h	2024-01-04 19:06:38 +00:00
corstone700	build(bl32): added check for AARCH32_SP	2023-08-24 14:22:34 -05:00
corstone1000	build(corstone1000): add CORSTONE1000_WITH_BL32 preprocessor flag	2024-02-21 14:37:14 +00:00
fvp	fix(cpus): workaround for Cortex-A715 erratum 2413290	2024-03-11 10:48:10 -05:00
fvp_r	chore(auth)!: remove CryptoCell-712/713 support	2023-11-08 10:42:33 +02:00
fvp_ve	refactor(bl2): make post image handling platform-specific	2023-10-30 10:29:03 +00:00
juno	refactor(juno): update SDS driver calls	2024-02-13 14:36:14 +01:00
morello	refactor(morello): update SDS driver calls	2024-02-13 14:36:14 +01:00
n1sdp	refactor(n1sdp): update SDS driver calls	2024-02-13 14:36:14 +01:00
neoverse_rd	refactor(cm): couple el2 registers with dependent feature flags	2024-03-07 14:50:23 +00:00
tc	Merge "fix(tc): do not use r0 for HW_CONFIG" into integration	2024-03-08 14:38:46 +01:00