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https://github.com/ARM-software/arm-trusted-firmware.git
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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
301 lines
9.5 KiB
C
301 lines
9.5 KiB
C
/*
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* Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32_I2C_H
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#define STM32_I2C_H
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#include <stdint.h>
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#include <lib/utils_def.h>
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/* Bit definition for I2C_CR1 register */
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#define I2C_CR1_PE BIT(0)
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#define I2C_CR1_TXIE BIT(1)
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#define I2C_CR1_RXIE BIT(2)
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#define I2C_CR1_ADDRIE BIT(3)
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#define I2C_CR1_NACKIE BIT(4)
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#define I2C_CR1_STOPIE BIT(5)
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#define I2C_CR1_TCIE BIT(6)
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#define I2C_CR1_ERRIE BIT(7)
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#define I2C_CR1_DNF GENMASK(11, 8)
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#define I2C_CR1_ANFOFF BIT(12)
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#define I2C_CR1_SWRST BIT(13)
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#define I2C_CR1_TXDMAEN BIT(14)
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#define I2C_CR1_RXDMAEN BIT(15)
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#define I2C_CR1_SBC BIT(16)
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#define I2C_CR1_NOSTRETCH BIT(17)
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#define I2C_CR1_WUPEN BIT(18)
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#define I2C_CR1_GCEN BIT(19)
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#define I2C_CR1_SMBHEN BIT(22)
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#define I2C_CR1_SMBDEN BIT(21)
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#define I2C_CR1_ALERTEN BIT(22)
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#define I2C_CR1_PECEN BIT(23)
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/* Bit definition for I2C_CR2 register */
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#define I2C_CR2_SADD GENMASK(9, 0)
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#define I2C_CR2_RD_WRN BIT(10)
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#define I2C_CR2_RD_WRN_OFFSET 10U
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#define I2C_CR2_ADD10 BIT(11)
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#define I2C_CR2_HEAD10R BIT(12)
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#define I2C_CR2_START BIT(13)
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#define I2C_CR2_STOP BIT(14)
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#define I2C_CR2_NACK BIT(15)
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#define I2C_CR2_NBYTES GENMASK(23, 16)
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#define I2C_CR2_NBYTES_OFFSET 16U
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#define I2C_CR2_RELOAD BIT(24)
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#define I2C_CR2_AUTOEND BIT(25)
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#define I2C_CR2_PECBYTE BIT(26)
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/* Bit definition for I2C_OAR1 register */
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#define I2C_OAR1_OA1 GENMASK(9, 0)
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#define I2C_OAR1_OA1MODE BIT(10)
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#define I2C_OAR1_OA1EN BIT(15)
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/* Bit definition for I2C_OAR2 register */
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#define I2C_OAR2_OA2 GENMASK(7, 1)
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#define I2C_OAR2_OA2MSK GENMASK(10, 8)
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#define I2C_OAR2_OA2NOMASK 0
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#define I2C_OAR2_OA2MASK01 BIT(8)
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#define I2C_OAR2_OA2MASK02 BIT(9)
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#define I2C_OAR2_OA2MASK03 GENMASK(9, 8)
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#define I2C_OAR2_OA2MASK04 BIT(10)
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#define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10))
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#define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10))
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#define I2C_OAR2_OA2MASK07 GENMASK(10, 8)
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#define I2C_OAR2_OA2EN BIT(15)
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/* Bit definition for I2C_TIMINGR register */
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#define I2C_TIMINGR_SCLL GENMASK(7, 0)
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#define I2C_TIMINGR_SCLH GENMASK(15, 8)
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#define I2C_TIMINGR_SDADEL GENMASK(19, 16)
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#define I2C_TIMINGR_SCLDEL GENMASK(23, 20)
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#define I2C_TIMINGR_PRESC GENMASK(31, 28)
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/* Bit definition for I2C_TIMEOUTR register */
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#define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0)
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#define I2C_TIMEOUTR_TIDLE BIT(12)
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#define I2C_TIMEOUTR_TIMOUTEN BIT(15)
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#define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16)
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#define I2C_TIMEOUTR_TEXTEN BIT(31)
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/* Bit definition for I2C_ISR register */
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#define I2C_ISR_TXE BIT(0)
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#define I2C_ISR_TXIS BIT(1)
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#define I2C_ISR_RXNE BIT(2)
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#define I2C_ISR_ADDR BIT(3)
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#define I2C_ISR_NACKF BIT(4)
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#define I2C_ISR_STOPF BIT(5)
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#define I2C_ISR_TC BIT(6)
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#define I2C_ISR_TCR BIT(7)
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#define I2C_ISR_BERR BIT(8)
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#define I2C_ISR_ARLO BIT(9)
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#define I2C_ISR_OVR BIT(10)
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#define I2C_ISR_PECERR BIT(11)
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#define I2C_ISR_TIMEOUT BIT(12)
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#define I2C_ISR_ALERT BIT(13)
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#define I2C_ISR_BUSY BIT(15)
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#define I2C_ISR_DIR BIT(16)
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#define I2C_ISR_ADDCODE GENMASK(23, 17)
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/* Bit definition for I2C_ICR register */
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#define I2C_ICR_ADDRCF BIT(3)
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#define I2C_ICR_NACKCF BIT(4)
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#define I2C_ICR_STOPCF BIT(5)
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#define I2C_ICR_BERRCF BIT(8)
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#define I2C_ICR_ARLOCF BIT(9)
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#define I2C_ICR_OVRCF BIT(10)
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#define I2C_ICR_PECCF BIT(11)
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#define I2C_ICR_TIMOUTCF BIT(12)
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#define I2C_ICR_ALERTCF BIT(13)
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struct stm32_i2c_init_s {
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uint32_t timing; /* Specifies the I2C_TIMINGR_register value
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* This parameter is calculated by referring
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* to I2C initialization section in Reference
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* manual.
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*/
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uint32_t own_address1; /* Specifies the first device own address.
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* This parameter can be a 7-bit or 10-bit
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* address.
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*/
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uint32_t addressing_mode; /* Specifies if 7-bit or 10-bit addressing
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* mode is selected.
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* This parameter can be a value of @ref
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* I2C_ADDRESSING_MODE.
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*/
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uint32_t dual_address_mode; /* Specifies if dual addressing mode is
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* selected.
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* This parameter can be a value of @ref
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* I2C_DUAL_ADDRESSING_MODE.
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*/
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uint32_t own_address2; /* Specifies the second device own address
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* if dual addressing mode is selected.
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* This parameter can be a 7-bit address.
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*/
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uint32_t own_address2_masks; /* Specifies the acknowledge mask address
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* second device own address if dual
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* addressing mode is selected.
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* This parameter can be a value of @ref
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* I2C_OWN_ADDRESS2_MASKS.
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*/
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uint32_t general_call_mode; /* Specifies if general call mode is
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* selected.
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* This parameter can be a value of @ref
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* I2C_GENERAL_CALL_ADDRESSING_MODE.
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*/
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uint32_t no_stretch_mode; /* Specifies if nostretch mode is
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* selected.
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* This parameter can be a value of @ref
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* I2C_NOSTRETCH_MODE.
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*/
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};
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enum i2c_state_e {
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I2C_STATE_RESET = 0x00U, /* Peripheral is not yet
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* initialized.
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*/
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I2C_STATE_READY = 0x20U, /* Peripheral Initialized
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* and ready for use.
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*/
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I2C_STATE_BUSY = 0x24U, /* An internal process is
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* ongoing.
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*/
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I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission process
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* is ongoing.
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*/
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I2C_STATE_BUSY_RX = 0x22U, /* Data Reception process
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* is ongoing.
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*/
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I2C_STATE_LISTEN = 0x28U, /* Address Listen Mode is
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* ongoing.
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*/
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I2C_STATE_BUSY_TX_LISTEN = 0x29U, /* Address Listen Mode
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* and Data Transmission
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* process is ongoing.
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*/
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I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /* Address Listen Mode
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* and Data Reception
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* process is ongoing.
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*/
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I2C_STATE_ABORT = 0x60U, /* Abort user request ongoing. */
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I2C_STATE_TIMEOUT = 0xA0U, /* Timeout state. */
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I2C_STATE_ERROR = 0xE0U /* Error. */
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};
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enum i2c_mode_e {
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I2C_MODE_NONE = 0x00U, /* No I2C communication on going. */
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I2C_MODE_MASTER = 0x10U, /* I2C communication is in Master Mode. */
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I2C_MODE_SLAVE = 0x20U, /* I2C communication is in Slave Mode. */
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I2C_MODE_MEM = 0x40U /* I2C communication is in Memory Mode. */
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};
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#define I2C_ERROR_NONE 0x00000000U /* No error */
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#define I2C_ERROR_BERR 0x00000001U /* BERR error */
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#define I2C_ERROR_ARLO 0x00000002U /* ARLO error */
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#define I2C_ERROR_AF 0x00000004U /* ACKF error */
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#define I2C_ERROR_OVR 0x00000008U /* OVR error */
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#define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */
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#define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */
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#define I2C_ERROR_SIZE 0x00000040U /* Size Management error */
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struct i2c_handle_s {
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uint32_t i2c_base_addr; /* Registers base address */
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struct stm32_i2c_init_s i2c_init; /* Communication parameters */
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uint8_t *p_buff; /* Pointer to transfer buffer */
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uint16_t xfer_size; /* Transfer size */
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uint16_t xfer_count; /* Transfer counter */
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uint32_t prev_state; /* Communication previous
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* state
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*/
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uint8_t lock; /* Locking object */
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enum i2c_state_e i2c_state; /* Communication state */
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enum i2c_mode_e i2c_mode; /* Communication mode */
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uint32_t i2c_err; /* Error code */
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};
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#define I2C_ADDRESSINGMODE_7BIT 0x00000001U
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#define I2C_ADDRESSINGMODE_10BIT 0x00000002U
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#define I2C_DUALADDRESS_DISABLE 0x00000000U
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#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
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#define I2C_GENERALCALL_DISABLE 0x00000000U
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#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
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#define I2C_NOSTRETCH_DISABLE 0x00000000U
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#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
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#define I2C_MEMADD_SIZE_8BIT 0x00000001U
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#define I2C_MEMADD_SIZE_16BIT 0x00000002U
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#define I2C_RELOAD_MODE I2C_CR2_RELOAD
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#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
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#define I2C_SOFTEND_MODE 0x00000000U
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#define I2C_NO_STARTSTOP 0x00000000U
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#define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP)
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#define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \
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I2C_CR2_RD_WRN)
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#define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START)
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#define I2C_FLAG_TXE I2C_ISR_TXE
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#define I2C_FLAG_TXIS I2C_ISR_TXIS
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#define I2C_FLAG_RXNE I2C_ISR_RXNE
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#define I2C_FLAG_ADDR I2C_ISR_ADDR
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#define I2C_FLAG_AF I2C_ISR_NACKF
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#define I2C_FLAG_STOPF I2C_ISR_STOPF
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#define I2C_FLAG_TC I2C_ISR_TC
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#define I2C_FLAG_TCR I2C_ISR_TCR
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#define I2C_FLAG_BERR I2C_ISR_BERR
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#define I2C_FLAG_ARLO I2C_ISR_ARLO
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#define I2C_FLAG_OVR I2C_ISR_OVR
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#define I2C_FLAG_PECERR I2C_ISR_PECERR
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#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
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#define I2C_FLAG_ALERT I2C_ISR_ALERT
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#define I2C_FLAG_BUSY I2C_ISR_BUSY
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#define I2C_FLAG_DIR I2C_ISR_DIR
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#define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \
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I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
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I2C_CR2_RD_WRN)
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#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
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#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
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int stm32_i2c_init(struct i2c_handle_s *hi2c);
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int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr,
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uint16_t mem_addr, uint16_t mem_add_size,
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uint8_t *p_data, uint16_t size, uint32_t timeout);
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int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr,
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uint16_t mem_addr, uint16_t mem_add_size,
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uint8_t *p_data, uint16_t size, uint32_t timeout);
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int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr,
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uint32_t trials, uint32_t timeout);
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int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c,
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uint32_t analog_filter);
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#endif /* STM32_I2C_H */
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