mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-18 10:34:19 +00:00
09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
569 lines
13 KiB
C
569 lines
13 KiB
C
/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "rcar_def.h"
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#include "cpg_registers.h"
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#include "iic_dvfs.h"
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#include "rcar_private.h"
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#define DVFS_RETRY_MAX (2U)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0B)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0E)
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#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_E (0x15)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05)
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#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_E (0x07)
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#define CPG_BIT_SMSTPCR9_DVFS (0x04000000)
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#define IIC_DVFS_REG_BASE (0xE60B0000)
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#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000)
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#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004)
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#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008)
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#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000C)
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#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010)
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#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014)
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#define IIC_DVFS_BIT_ICSR_BUSY (0x10)
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#define IIC_DVFS_BIT_ICSR_AL (0x08)
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#define IIC_DVFS_BIT_ICSR_TACK (0x04)
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#define IIC_DVFS_BIT_ICSR_WAIT (0x02)
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#define IIC_DVFS_BIT_ICSR_DTE (0x01)
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#define IIC_DVFS_BIT_ICCR_ENABLE (0x80)
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#define IIC_DVFS_SET_ICCR_START (0x94)
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#define IIC_DVFS_SET_ICCR_STOP (0x90)
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#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94)
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#define IIC_DVFS_SET_ICCR_CHANGE (0x81)
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#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0)
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#define IIC_DVFS_BIT_ICIC_TACKE (0x04)
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#define IIC_DVFS_BIT_ICIC_WAITE (0x02)
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#define IIC_DVFS_BIT_ICIC_DTEE (0x01)
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#define DVFS_READ_MODE (0x01)
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#define DVFS_WRITE_MODE (0x00)
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#define IIC_DVFS_SET_DUMMY (0x52)
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#define IIC_DVFS_SET_BUSY_LOOP (500000000U)
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typedef enum {
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DVFS_START = 0,
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DVFS_STOP,
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DVFS_RETRANSMIT,
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DVFS_READ,
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DVFS_STOP_READ,
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DVFS_SET_SLAVE_READ,
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DVFS_SET_SLAVE,
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DVFS_WRITE_ADDR,
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DVFS_WRITE_DATA,
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DVFS_CHANGE_SEND_TO_RECIEVE,
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DVFS_DONE,
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} DVFS_STATE_T;
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#define DVFS_PROCESS (1)
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#define DVFS_COMPLETE (0)
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#define DVFS_ERROR (-1)
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#if IMAGE_BL31
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#define IIC_DVFS_FUNC(__name, ...) \
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static int32_t __attribute__ ((section (".system_ram"))) \
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dvfs_ ##__name(__VA_ARGS__)
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#define RCAR_DVFS_API(__name, ...) \
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int32_t __attribute__ ((section (".system_ram"))) \
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rcar_iic_dvfs_ ##__name(__VA_ARGS__)
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#else
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#define IIC_DVFS_FUNC(__name, ...) \
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static int32_t dvfs_ ##__name(__VA_ARGS__)
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#define RCAR_DVFS_API(__name, ...) \
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int32_t rcar_iic_dvfs_ ##__name(__VA_ARGS__)
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#endif
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IIC_DVFS_FUNC(check_error, DVFS_STATE_T *state, uint32_t *err, uint8_t mode)
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{
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uint8_t icsr_al = 0, icsr_tack = 0;
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uint8_t reg, stop;
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uint32_t i = 0;
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stop = mode == DVFS_READ_MODE ? IIC_DVFS_SET_ICCR_STOP_READ :
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IIC_DVFS_SET_ICCR_STOP;
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reg = mmio_read_8(IIC_DVFS_REG_ICSR);
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icsr_al = (reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL;
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icsr_tack = (reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK;
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if (icsr_al == 0 && icsr_tack == 0)
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return DVFS_PROCESS;
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if (icsr_al) {
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_AL;
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mmio_write_8(IIC_DVFS_REG_ICSR, reg);
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if (*state == DVFS_SET_SLAVE)
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mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY);
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do {
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
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IIC_DVFS_BIT_ICSR_WAIT;
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} while (reg == 0);
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mmio_write_8(IIC_DVFS_REG_ICCR, stop);
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
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mmio_write_8(IIC_DVFS_REG_ICSR, reg);
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i = 0;
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do {
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) &
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IIC_DVFS_BIT_ICSR_BUSY;
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if (reg == 0)
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break;
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if (i++ > IIC_DVFS_SET_BUSY_LOOP)
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panic();
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} while (1);
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mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U);
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(*err)++;
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if (*err > DVFS_RETRY_MAX)
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return DVFS_ERROR;
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*state = DVFS_START;
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return DVFS_PROCESS;
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}
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/* icsr_tack */
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mmio_write_8(IIC_DVFS_REG_ICCR, stop);
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reg = mmio_read_8(IIC_DVFS_REG_ICIC);
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reg &= ~(IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE);
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mmio_write_8(IIC_DVFS_REG_ICIC, reg);
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reg = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_TACK;
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mmio_write_8(IIC_DVFS_REG_ICSR, reg);
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i = 0;
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while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) != 0) {
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if (i++ > IIC_DVFS_SET_BUSY_LOOP)
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panic();
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}
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mmio_write_8(IIC_DVFS_REG_ICCR, 0);
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(*err)++;
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if (*err > DVFS_RETRY_MAX)
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return DVFS_ERROR;
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*state = DVFS_START;
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return DVFS_PROCESS;
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}
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IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
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{
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uint8_t iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_E;
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uint8_t icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_E;
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int32_t result = DVFS_PROCESS;
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uint32_t reg, lsi_product;
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uint8_t mode;
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mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
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mmio_write_8(IIC_DVFS_REG_ICCR, mode);
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lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
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if (lsi_product == RCAR_PRODUCT_E3)
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goto start;
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reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;
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switch (reg) {
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case MD14_MD13_TYPE_0:
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iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_0;
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icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_0;
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break;
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case MD14_MD13_TYPE_1:
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iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_1;
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icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_1;
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break;
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case MD14_MD13_TYPE_2:
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iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_2;
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icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_2;
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break;
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default:
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iccl = IIC_DVFS_SET_ICCL_EXTAL_TYPE_3;
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icch = IIC_DVFS_SET_ICCH_EXTAL_TYPE_3;
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break;
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}
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start:
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mmio_write_8(IIC_DVFS_REG_ICCL, iccl);
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mmio_write_8(IIC_DVFS_REG_ICCH, icch);
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mode = mmio_read_8(IIC_DVFS_REG_ICIC)
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| IIC_DVFS_BIT_ICIC_TACKE
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| IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE;
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mmio_write_8(IIC_DVFS_REG_ICIC, mode);
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mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_START);
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*state = DVFS_SET_SLAVE;
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return result;
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}
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IIC_DVFS_FUNC(set_slave, DVFS_STATE_T * state, uint32_t *err, uint8_t slave)
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{
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uint8_t mode;
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int32_t result;
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uint8_t address;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
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if (mode != IIC_DVFS_BIT_ICSR_DTE)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
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mmio_write_8(IIC_DVFS_REG_ICIC, mode);
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address = slave << 1;
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mmio_write_8(IIC_DVFS_REG_ICDR, address);
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*state = DVFS_WRITE_ADDR;
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return result;
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}
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IIC_DVFS_FUNC(write_addr, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_addr)
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{
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uint8_t mode;
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int32_t result;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
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if (mode != IIC_DVFS_BIT_ICSR_WAIT)
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return result;
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mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
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mmio_write_8(IIC_DVFS_REG_ICSR, mode);
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*state = DVFS_WRITE_DATA;
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return result;
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}
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IIC_DVFS_FUNC(write_data, DVFS_STATE_T *state, uint32_t *err, uint8_t reg_data)
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{
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int32_t result;
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uint8_t mode;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
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if (mode != IIC_DVFS_BIT_ICSR_WAIT)
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return result;
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mmio_write_8(IIC_DVFS_REG_ICDR, reg_data);
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
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mmio_write_8(IIC_DVFS_REG_ICSR, mode);
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*state = DVFS_STOP;
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return result;
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}
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IIC_DVFS_FUNC(stop, DVFS_STATE_T *state, uint32_t *err)
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{
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int32_t result;
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uint8_t mode;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
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if (mode != IIC_DVFS_BIT_ICSR_WAIT)
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return result;
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mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP);
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
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mmio_write_8(IIC_DVFS_REG_ICSR, mode);
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*state = DVFS_DONE;
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return result;
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}
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IIC_DVFS_FUNC(done, void)
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{
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uint32_t i;
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for (i = 0; i < IIC_DVFS_SET_BUSY_LOOP; i++) {
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if (mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY)
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continue;
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goto done;
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}
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panic();
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done:
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mmio_write_8(IIC_DVFS_REG_ICCR, 0);
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return DVFS_COMPLETE;
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}
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IIC_DVFS_FUNC(write_reg_addr_read, DVFS_STATE_T *state, uint32_t *err,
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uint8_t reg_addr)
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{
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int32_t result;
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uint8_t mode;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
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if (mode != IIC_DVFS_BIT_ICSR_WAIT)
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return result;
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mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr);
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
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mmio_write_8(IIC_DVFS_REG_ICSR, mode);
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*state = DVFS_RETRANSMIT;
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return result;
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}
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IIC_DVFS_FUNC(retransmit, DVFS_STATE_T *state, uint32_t *err)
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{
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int32_t result;
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uint8_t mode;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
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if (mode != IIC_DVFS_BIT_ICSR_WAIT)
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return result;
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mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION);
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
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mmio_write_8(IIC_DVFS_REG_ICSR, mode);
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mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
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mmio_write_8(IIC_DVFS_REG_ICIC, mode);
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*state = DVFS_SET_SLAVE_READ;
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return result;
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}
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IIC_DVFS_FUNC(set_slave_read, DVFS_STATE_T *state, uint32_t *err,
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uint8_t slave)
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{
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uint8_t address;
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int32_t result;
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uint8_t mode;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
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if (mode != IIC_DVFS_BIT_ICSR_DTE)
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return result;
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mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
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mmio_write_8(IIC_DVFS_REG_ICIC, mode);
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address = ((uint8_t) (slave << 1) + DVFS_READ_MODE);
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mmio_write_8(IIC_DVFS_REG_ICDR, address);
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*state = DVFS_CHANGE_SEND_TO_RECIEVE;
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return result;
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}
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IIC_DVFS_FUNC(change_send_to_recieve, DVFS_STATE_T *state, uint32_t *err)
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{
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int32_t result;
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uint8_t mode;
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result = dvfs_check_error(state, err, DVFS_WRITE_MODE);
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if (result == DVFS_ERROR)
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return result;
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|
|
|
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
|
if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
|
return result;
|
|
|
|
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE);
|
|
|
|
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
|
|
mmio_write_8(IIC_DVFS_REG_ICSR, mode);
|
|
|
|
*state = DVFS_STOP_READ;
|
|
|
|
return result;
|
|
}
|
|
|
|
IIC_DVFS_FUNC(stop_read, DVFS_STATE_T *state, uint32_t *err)
|
|
{
|
|
int32_t result;
|
|
uint8_t mode;
|
|
|
|
result = dvfs_check_error(state, err, DVFS_READ_MODE);
|
|
if (result == DVFS_ERROR)
|
|
return result;
|
|
|
|
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT;
|
|
if (mode != IIC_DVFS_BIT_ICSR_WAIT)
|
|
return result;
|
|
|
|
mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ);
|
|
|
|
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & ~IIC_DVFS_BIT_ICSR_WAIT;
|
|
mmio_write_8(IIC_DVFS_REG_ICSR, mode);
|
|
|
|
mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE;
|
|
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
|
|
|
|
*state = DVFS_READ;
|
|
|
|
return result;
|
|
}
|
|
|
|
IIC_DVFS_FUNC(read, DVFS_STATE_T *state, uint8_t *reg_data)
|
|
{
|
|
uint8_t mode;
|
|
|
|
mode = mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_DTE;
|
|
if (mode != IIC_DVFS_BIT_ICSR_DTE)
|
|
return DVFS_PROCESS;
|
|
|
|
mode = mmio_read_8(IIC_DVFS_REG_ICIC) & ~IIC_DVFS_BIT_ICIC_DTEE;
|
|
mmio_write_8(IIC_DVFS_REG_ICIC, mode);
|
|
|
|
*reg_data = mmio_read_8(IIC_DVFS_REG_ICDR);
|
|
*state = DVFS_DONE;
|
|
|
|
return DVFS_PROCESS;
|
|
}
|
|
|
|
RCAR_DVFS_API(send, uint8_t slave, uint8_t reg_addr, uint8_t reg_data)
|
|
{
|
|
DVFS_STATE_T state = DVFS_START;
|
|
int32_t result = DVFS_PROCESS;
|
|
uint32_t err = 0;
|
|
|
|
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
|
|
mmio_write_8(IIC_DVFS_REG_ICCR, 0);
|
|
again:
|
|
switch (state) {
|
|
case DVFS_START:
|
|
result = dvfs_start(&state);
|
|
break;
|
|
case DVFS_SET_SLAVE:
|
|
result = dvfs_set_slave(&state, &err, slave);
|
|
break;
|
|
case DVFS_WRITE_ADDR:
|
|
result = dvfs_write_addr(&state, &err, reg_addr);
|
|
break;
|
|
case DVFS_WRITE_DATA:
|
|
result = dvfs_write_data(&state, &err, reg_data);
|
|
break;
|
|
case DVFS_STOP:
|
|
result = dvfs_stop(&state, &err);
|
|
break;
|
|
case DVFS_DONE:
|
|
result = dvfs_done();
|
|
break;
|
|
default:
|
|
panic();
|
|
break;
|
|
}
|
|
|
|
if (result == DVFS_PROCESS)
|
|
goto again;
|
|
|
|
return result;
|
|
}
|
|
|
|
RCAR_DVFS_API(receive, uint8_t slave, uint8_t reg, uint8_t *data)
|
|
{
|
|
DVFS_STATE_T state = DVFS_START;
|
|
int32_t result = DVFS_PROCESS;
|
|
uint32_t err = 0;
|
|
|
|
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
|
|
mmio_write_8(IIC_DVFS_REG_ICCR, 0);
|
|
again:
|
|
switch (state) {
|
|
case DVFS_START:
|
|
result = dvfs_start(&state);
|
|
break;
|
|
case DVFS_SET_SLAVE:
|
|
result = dvfs_set_slave(&state, &err, slave);
|
|
break;
|
|
case DVFS_WRITE_ADDR:
|
|
result = dvfs_write_reg_addr_read(&state, &err, reg);
|
|
break;
|
|
case DVFS_RETRANSMIT:
|
|
result = dvfs_retransmit(&state, &err);
|
|
break;
|
|
case DVFS_SET_SLAVE_READ:
|
|
result = dvfs_set_slave_read(&state, &err, slave);
|
|
break;
|
|
case DVFS_CHANGE_SEND_TO_RECIEVE:
|
|
result = dvfs_change_send_to_recieve(&state, &err);
|
|
break;
|
|
case DVFS_STOP_READ:
|
|
result = dvfs_stop_read(&state, &err);
|
|
break;
|
|
case DVFS_READ:
|
|
result = dvfs_read(&state, data);
|
|
break;
|
|
case DVFS_DONE:
|
|
result = dvfs_done();
|
|
break;
|
|
default:
|
|
panic();
|
|
break;
|
|
}
|
|
|
|
if (result == DVFS_PROCESS)
|
|
goto again;
|
|
|
|
return result;
|
|
}
|