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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
149 lines
3.8 KiB
C
149 lines
3.8 KiB
C
/*
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* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include "rcar_def.h"
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#include "cpg_registers.h"
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#include "rcar_private.h"
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/* DMA CHANNEL setting (0/16/32) */
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#define DMA_CH 0
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#if (DMA_CH == 0)
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#define SYS_DMAC_BIT ((uint32_t)1U << 19U)
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#define DMA_BASE (0xE6700000U)
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#elif (DMA_CH == 16)
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#define SYS_DMAC_BIT ((uint32_t)1U << 18U)
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#define DMA_BASE (0xE7300000U)
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#elif (DMA_CH == 32)
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#define SYS_DMAC_BIT ((uint32_t)1U << 17U)
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#define DMA_BASE (0xE7320000U)
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#else
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#define SYS_DMAC_BIT ((uint32_t)1U << 19U)
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#define DMA_BASE (0xE6700000U)
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#endif
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/* DMA operation */
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#define DMA_DMAOR (DMA_BASE + 0x0060U)
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/* DMA secure control */
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#define DMA_DMASEC (DMA_BASE + 0x0030U)
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/* DMA channel clear */
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#define DMA_DMACHCLR (DMA_BASE + 0x0080U)
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/* DMA source address */
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#define DMA_DMASAR (DMA_BASE + 0x8000U)
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/* DMA destination address */
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#define DMA_DMADAR (DMA_BASE + 0x8004U)
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/* DMA transfer count */
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#define DMA_DMATCR (DMA_BASE + 0x8008U)
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/* DMA channel control */
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#define DMA_DMACHCR (DMA_BASE + 0x800CU)
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/* DMA fixed destination address */
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#define DMA_DMAFIXDAR (DMA_BASE + 0x8014U)
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#define DMA_USE_CHANNEL (0x00000001U)
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#define DMAOR_INITIAL (0x0301U)
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#define DMACHCLR_CH_ALL (0x0000FFFFU)
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#define DMAFIXDAR_32BIT_SHIFT (32U)
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#define DMAFIXDAR_DAR_MASK (0x000000FFU)
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#define DMADAR_BOUNDARY_ADDR (0x100000000ULL)
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#define DMATCR_CNT_SHIFT (6U)
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#define DMATCR_MAX (0x00FFFFFFU)
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#define DMACHCR_TRN_MODE (0x00105409U)
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#define DMACHCR_DE_BIT (0x00000001U)
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#define DMACHCR_TE_BIT (0x00000002U)
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#define DMACHCR_CHE_BIT (0x80000000U)
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#define DMA_SIZE_UNIT FLASH_TRANS_SIZE_UNIT
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#define DMA_FRACTION_MASK (0xFFU)
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#define DMA_DST_LIMIT (0x10000000000ULL)
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/* transfer length limit */
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#define DMA_LENGTH_LIMIT ((DMATCR_MAX * (1U << DMATCR_CNT_SHIFT)) \
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& ~DMA_FRACTION_MASK)
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static void dma_enable(void)
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{
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mstpcr_write(CPG_SMSTPCR2, CPG_MSTPSR2, SYS_DMAC_BIT);
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}
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static void dma_setup(void)
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{
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mmio_write_16(DMA_DMAOR, 0);
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mmio_write_32(DMA_DMACHCLR, DMACHCLR_CH_ALL);
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}
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static void dma_start(uintptr_t dst, uint32_t src, uint32_t len)
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{
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mmio_write_16(DMA_DMAOR, DMAOR_INITIAL);
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mmio_write_32(DMA_DMAFIXDAR, (dst >> DMAFIXDAR_32BIT_SHIFT) &
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DMAFIXDAR_DAR_MASK);
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mmio_write_32(DMA_DMADAR, dst & UINT32_MAX);
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mmio_write_32(DMA_DMASAR, src);
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mmio_write_32(DMA_DMATCR, len >> DMATCR_CNT_SHIFT);
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mmio_write_32(DMA_DMASEC, DMA_USE_CHANNEL);
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mmio_write_32(DMA_DMACHCR, DMACHCR_TRN_MODE);
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}
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static void dma_end(void)
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{
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while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_TE_BIT) == 0) {
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if ((mmio_read_32(DMA_DMACHCR) & DMACHCR_CHE_BIT) != 0U) {
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ERROR("BL2: DMA - Channel Address Error\n");
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panic();
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break;
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}
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}
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/* DMA transfer Disable */
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mmio_clrbits_32(DMA_DMACHCR, DMACHCR_DE_BIT);
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while ((mmio_read_32(DMA_DMACHCR) & DMACHCR_DE_BIT) != 0)
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;
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mmio_write_32(DMA_DMASEC, 0);
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mmio_write_16(DMA_DMAOR, 0);
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mmio_write_32(DMA_DMACHCLR, DMA_USE_CHANNEL);
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}
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void rcar_dma_exec(uintptr_t dst, uint32_t src, uint32_t len)
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{
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uint32_t dma_len = len;
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if (len & DMA_FRACTION_MASK)
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dma_len = (len + DMA_SIZE_UNIT) & ~DMA_FRACTION_MASK;
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if (!dma_len || dma_len > DMA_LENGTH_LIMIT) {
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ERROR("BL2: DMA - size invalid, length (0x%x)\n", dma_len);
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panic();
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}
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if (src & DMA_FRACTION_MASK) {
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ERROR("BL2: DMA - source address invalid (0x%x), "
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"length (0x%x)\n", src, dma_len);
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panic();
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}
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if ((dst & UINT32_MAX) + dma_len > DMADAR_BOUNDARY_ADDR ||
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(dst + dma_len > DMA_DST_LIMIT) ||
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(dst & DMA_FRACTION_MASK)) {
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ERROR("BL2: DMA - destination address invalid (0x%lx), "
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"length (0x%x)\n", dst, dma_len);
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panic();
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}
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dma_start(dst, src, dma_len);
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dma_end();
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}
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void rcar_dma_init(void)
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{
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dma_enable();
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dma_setup();
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}
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