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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
102 lines
2.7 KiB
C
102 lines
2.7 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <drivers/delay_timer.h>
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#include <drivers/marvell/aro.h>
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#include <lib/mmio.h>
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#include <a8k_plat_def.h>
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/* Notify bootloader on DRAM setup */
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#define AP807_CPU_ARO_CTRL(cluster) \
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(MVEBU_RFU_BASE + 0x82A8 + (0xA58 * (cluster)))
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/* 0 - ARO clock is enabled, 1 - ARO clock is disabled */
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#define AP807_CPU_ARO_CLK_EN_OFFSET 0
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#define AP807_CPU_ARO_CLK_EN_MASK (0x1 << AP807_CPU_ARO_CLK_EN_OFFSET)
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/* 0 - ARO is the clock source, 1 - PLL is the clock source */
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#define AP807_CPU_ARO_SEL_PLL_OFFSET 5
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#define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET)
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/* AP807 clusters count */
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#define AP807_CLUSTER_NUM 2
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/* PLL frequency values */
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#define PLL_FREQ_1200 0x2AE5F002 /* 1200 */
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#define PLL_FREQ_2000 0x2FC9F002 /* 2000 */
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#define PLL_FREQ_2200 0x2AC57001 /* 2200 */
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#define PLL_FREQ_2400 0x2AE5F001 /* 2400 */
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/* CPU PLL control registers */
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#define AP807_CPU_PLL_CTRL(cluster) \
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(MVEBU_RFU_BASE + 0x82E0 + (0x8 * (cluster)))
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#define AP807_CPU_PLL_PARAM(cluster) AP807_CPU_PLL_CTRL(cluster)
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#define AP807_CPU_PLL_CFG(cluster) (AP807_CPU_PLL_CTRL(cluster) + 0x4)
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#define AP807_CPU_PLL_CFG_BYPASS_MODE (0x1)
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#define AP807_CPU_PLL_CFG_USE_REG_FILE (0x1 << 9)
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static void pll_set_freq(unsigned int freq_val)
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{
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int i;
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for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_CFG_USE_REG_FILE);
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_CFG_USE_REG_FILE |
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AP807_CPU_PLL_CFG_BYPASS_MODE);
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mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val);
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_CFG_USE_REG_FILE);
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}
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}
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/* Switch to ARO from PLL in ap807 */
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static void aro_to_pll(void)
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{
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unsigned int reg;
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int i;
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for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
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/* switch from ARO to PLL */
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reg = mmio_read_32(AP807_CPU_ARO_CTRL(i));
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reg |= AP807_CPU_ARO_SEL_PLL_MASK;
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mmio_write_32(AP807_CPU_ARO_CTRL(i), reg);
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mdelay(100);
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/* disable ARO clk driver */
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reg = mmio_read_32(AP807_CPU_ARO_CTRL(i));
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reg |= (AP807_CPU_ARO_CLK_EN_MASK);
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mmio_write_32(AP807_CPU_ARO_CTRL(i), reg);
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}
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}
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/* switch from ARO to PLL
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* in case of default frequency option, configure PLL registers
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* to be aligned with new default frequency.
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*/
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void ap807_clocks_init(unsigned int freq_option)
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{
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/* Switch from ARO to PLL */
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aro_to_pll();
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/* Modifications in frequency table:
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* 0x0: 764x: change to 2000 MHz.
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* 0x2: 744x change to 1800 MHz, 764x change to 2200/2400.
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* 0x3: 3900/744x/764x change to 1200 MHz.
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*/
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switch (freq_option) {
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case CPU_2000_DDR_1200_RCLK_1200:
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pll_set_freq(PLL_FREQ_2000);
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break;
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default:
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break;
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}
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}
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