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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
60 lines
1.4 KiB
C
60 lines
1.4 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <cdefs.h>
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#include <stdbool.h>
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#include <drivers/arm/smmu_v3.h>
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#include <lib/mmio.h>
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static inline uint32_t __init smmuv3_read_s_idr1(uintptr_t base)
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{
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return mmio_read_32(base + SMMU_S_IDR1);
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}
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static inline uint32_t __init smmuv3_read_s_init(uintptr_t base)
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{
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return mmio_read_32(base + SMMU_S_INIT);
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}
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static inline void __init smmuv3_write_s_init(uintptr_t base, uint32_t value)
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{
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mmio_write_32(base + SMMU_S_INIT, value);
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}
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/* Test for pending invalidate */
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static inline bool smmuv3_inval_pending(uintptr_t base)
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{
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return (smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK) != 0U;
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}
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/*
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* Initialize the SMMU by invalidating all secure caches and TLBs.
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*
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* Returns 0 on success, and -1 on failure.
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*/
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int __init smmuv3_init(uintptr_t smmu_base)
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{
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uint32_t idr1_reg;
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/*
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* Invalidation of secure caches and TLBs is required only if the SMMU
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* supports secure state. If not, it's implementation defined as to how
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* SMMU_S_INIT register is accessed.
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*/
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idr1_reg = smmuv3_read_s_idr1(smmu_base);
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if (((idr1_reg >> SMMU_S_IDR1_SECURE_IMPL_SHIFT) &
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SMMU_S_IDR1_SECURE_IMPL_MASK) == 0U) {
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return -1;
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}
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/* Initiate invalidation, and wait for it to finish */
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smmuv3_write_s_init(smmu_base, SMMU_S_INIT_INV_ALL_MASK);
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while (smmuv3_inval_pending(smmu_base))
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;
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return 0;
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}
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