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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* Driver for implementation defined features that are identical in ARM GICv3
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* implementations (GIC-500 and GIC-600 for now). This driver only overrides
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* APIs that are different to those generic ones in GICv3 driver.
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <drivers/arm/arm_gicv3_common.h>
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#include <drivers/arm/gicv3.h>
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#include "gicv3_private.h"
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/*
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* Flush the internal GIC cache of the LPIs pending tables to memory before
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* saving the state of the Redistributor. This is required before powering off
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* the GIC when the pending status must be preserved.
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* `rdist_proc_num` is the processor number corresponding to the Redistributor of the
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* current CPU.
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*/
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void arm_gicv3_distif_pre_save(unsigned int rdist_proc_num)
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{
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uintptr_t gicr_base = 0;
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assert(gicv3_driver_data);
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assert(gicv3_driver_data->rdistif_base_addrs);
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/*
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* The GICR_WAKER.Sleep bit should be set only when both
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* GICR_WAKER.ChildrenAsleep and GICR_WAKER.ProcessorSleep are set on
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* all the Redistributors.
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*/
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for (unsigned int i = 0; i < gicv3_driver_data->rdistif_num; i++) {
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gicr_base = gicv3_driver_data->rdistif_base_addrs[i];
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assert(gicr_base);
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assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT);
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assert(gicr_read_waker(gicr_base) & WAKER_PS_BIT);
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}
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gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num];
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/*
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* According to the TRM, there is only one instance of the
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* GICR_WAKER.Sleep and GICR_WAKER.Quiescent bits that can be accessed
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* through any of the Redistributor.
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*/
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/*
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* Set GICR_WAKER.Sleep
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* After this point, the system must be configured so that the
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* wake_request signals for the right cores are asserted when a wakeup
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* interrupt is detected. The GIC will not be able to do that anymore
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* when the GICR_WAKER.Sleep bit is set to 1.
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*/
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gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_SL_BIT);
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/* Wait until the GICR_WAKER.Quiescent bit is set */
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while (!(gicr_read_waker(gicr_base) & WAKER_QSC_BIT))
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;
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}
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/*
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* Allow the LPIs pending state to be read back from the tables in memory after
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* having restored the state of the GIC Redistributor.
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*/
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void arm_gicv3_distif_post_restore(unsigned int rdist_proc_num)
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{
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uintptr_t gicr_base;
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assert(gicv3_driver_data);
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assert(gicv3_driver_data->rdistif_base_addrs);
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/*
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* According to the TRM, there is only one instance of the
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* GICR_WAKER.Sleep and GICR_WAKER.Quiescent bits that can be accessed
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* through any of the Redistributor.
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*/
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gicr_base = gicv3_driver_data->rdistif_base_addrs[rdist_proc_num];
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assert(gicr_base);
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/*
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* If the GIC had power removed, the GICR_WAKER state will be reset.
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* Since the GICR_WAKER.Sleep and GICR_WAKER.Quiescent bits are cleared,
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* we can exit early. This also prevents the following assert from
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* erroneously triggering.
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*/
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if (!(gicr_read_waker(gicr_base) & WAKER_SL_BIT))
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return;
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/*
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* Writes to GICR_WAKER.Sleep bit are ignored if GICR_WAKER.Quiescent
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* bit is not set. We should be alright on power on path, therefore
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* coming out of sleep and Quiescent should be set, but we assert in
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* case.
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*/
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assert(gicr_read_waker(gicr_base) & WAKER_QSC_BIT);
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/* Clear GICR_WAKER.Sleep */
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gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_SL_BIT);
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/*
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* We don't know if the effects of setting GICR_WAKER.Sleep bit is
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* instantaneous, so we wait until the interface is not Quiescent
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* anymore.
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*/
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while (gicr_read_waker(gicr_base) & WAKER_QSC_BIT)
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;
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}
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