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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
150 lines
4 KiB
C
150 lines
4 KiB
C
/*
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* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GICV2_PRIVATE_H
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#define GICV2_PRIVATE_H
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#include <stdint.h>
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#include <drivers/arm/gicv2.h>
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#include <lib/mmio.h>
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/*******************************************************************************
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* Private function prototypes
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******************************************************************************/
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void gicv2_spis_configure_defaults(uintptr_t gicd_base);
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void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
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const interrupt_prop_t *interrupt_props,
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unsigned int interrupt_props_num);
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void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
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const interrupt_prop_t *interrupt_props,
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unsigned int interrupt_props_num);
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unsigned int gicv2_get_cpuif_id(uintptr_t base);
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/*******************************************************************************
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* GIC Distributor interface accessors for reading entire registers
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******************************************************************************/
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static inline unsigned int gicd_read_pidr2(uintptr_t base)
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{
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return mmio_read_32(base + GICD_PIDR2_GICV2);
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}
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/*******************************************************************************
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* GIC Distributor interface accessors for writing entire registers
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******************************************************************************/
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static inline unsigned int gicd_get_itargetsr(uintptr_t base, unsigned int id)
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{
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return mmio_read_8(base + GICD_ITARGETSR + id);
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}
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static inline void gicd_set_itargetsr(uintptr_t base, unsigned int id,
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unsigned int target)
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{
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uint8_t val = target & GIC_TARGET_CPU_MASK;
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mmio_write_8(base + GICD_ITARGETSR + id, val);
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}
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static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICD_SGIR, val);
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}
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/*******************************************************************************
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* GIC CPU interface accessors for reading entire registers
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******************************************************************************/
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static inline unsigned int gicc_read_ctlr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_CTLR);
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}
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static inline unsigned int gicc_read_pmr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_PMR);
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}
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static inline unsigned int gicc_read_BPR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_BPR);
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}
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static inline unsigned int gicc_read_IAR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_IAR);
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}
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static inline unsigned int gicc_read_EOIR(uintptr_t base)
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{
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return mmio_read_32(base + GICC_EOIR);
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}
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static inline unsigned int gicc_read_hppir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_HPPIR);
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}
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static inline unsigned int gicc_read_ahppir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_AHPPIR);
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}
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static inline unsigned int gicc_read_dir(uintptr_t base)
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{
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return mmio_read_32(base + GICC_DIR);
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}
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static inline unsigned int gicc_read_iidr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_IIDR);
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}
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static inline unsigned int gicc_read_rpr(uintptr_t base)
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{
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return mmio_read_32(base + GICC_RPR);
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}
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/*******************************************************************************
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* GIC CPU interface accessors for writing entire registers
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******************************************************************************/
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static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_CTLR, val);
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}
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static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_PMR, val);
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}
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static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_BPR, val);
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}
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static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_IAR, val);
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}
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static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_EOIR, val);
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}
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static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_HPPIR, val);
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}
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static inline void gicc_write_dir(uintptr_t base, unsigned int val)
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{
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mmio_write_32(base + GICC_DIR, val);
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}
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#endif /* GICV2_PRIVATE_H */
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