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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
91 lines
3 KiB
C
91 lines
3 KiB
C
/*
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* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <plat/common/platform.h>
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#include "tsp_private.h"
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/*******************************************************************************
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* Data structure to keep track of per-cpu secure generic timer context across
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* power management operations.
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******************************************************************************/
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typedef struct timer_context {
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uint64_t cval;
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uint32_t ctl;
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} timer_context_t;
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static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* This function initializes the generic timer to fire every 0.5 second
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******************************************************************************/
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void tsp_generic_timer_start(void)
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{
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uint64_t cval;
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uint32_t ctl = 0;
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/* The timer will fire every 0.5 second */
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cval = read_cntpct_el0() + (read_cntfrq_el0() >> 1);
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write_cntps_cval_el1(cval);
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/* Enable the secure physical timer */
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set_cntp_ctl_enable(ctl);
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write_cntps_ctl_el1(ctl);
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}
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/*******************************************************************************
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* This function deasserts the timer interrupt and sets it up again
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******************************************************************************/
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void tsp_generic_timer_handler(void)
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{
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/* Ensure that the timer did assert the interrupt */
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assert(get_cntp_ctl_istatus(read_cntps_ctl_el1()));
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/*
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* Disable the timer and reprogram it. The barriers ensure that there is
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* no reordering of instructions around the reprogramming code.
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*/
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isb();
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write_cntps_ctl_el1(0);
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tsp_generic_timer_start();
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isb();
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}
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/*******************************************************************************
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* This function deasserts the timer interrupt prior to cpu power down
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******************************************************************************/
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void tsp_generic_timer_stop(void)
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{
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/* Disable the timer */
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write_cntps_ctl_el1(0);
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}
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/*******************************************************************************
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* This function saves the timer context prior to cpu suspension
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******************************************************************************/
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void tsp_generic_timer_save(void)
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{
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uint32_t linear_id = plat_my_core_pos();
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pcpu_timer_context[linear_id].cval = read_cntps_cval_el1();
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pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1();
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flush_dcache_range((uint64_t) &pcpu_timer_context[linear_id],
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sizeof(pcpu_timer_context[linear_id]));
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}
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/*******************************************************************************
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* This function restores the timer context post cpu resummption
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******************************************************************************/
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void tsp_generic_timer_restore(void)
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{
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uint32_t linear_id = plat_my_core_pos();
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write_cntps_cval_el1(pcpu_timer_context[linear_id].cval);
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write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl);
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}
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