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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
162 lines
4 KiB
ArmAsm
162 lines
4 KiB
ArmAsm
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl32/tsp/tsp.h>
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#include <common/bl_common.h>
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/* ----------------------------------------------------
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* The caller-saved registers x0-x18 and LR are saved
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* here.
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* ----------------------------------------------------
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*/
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#define SCRATCH_REG_SIZE #(20 * 8)
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.macro save_caller_regs_and_lr
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sub sp, sp, SCRATCH_REG_SIZE
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stp x0, x1, [sp]
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stp x2, x3, [sp, #0x10]
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stp x4, x5, [sp, #0x20]
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stp x6, x7, [sp, #0x30]
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stp x8, x9, [sp, #0x40]
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stp x10, x11, [sp, #0x50]
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stp x12, x13, [sp, #0x60]
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stp x14, x15, [sp, #0x70]
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stp x16, x17, [sp, #0x80]
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stp x18, x30, [sp, #0x90]
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.endm
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.macro restore_caller_regs_and_lr
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ldp x0, x1, [sp]
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ldp x2, x3, [sp, #0x10]
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ldp x4, x5, [sp, #0x20]
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ldp x6, x7, [sp, #0x30]
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ldp x8, x9, [sp, #0x40]
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ldp x10, x11, [sp, #0x50]
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ldp x12, x13, [sp, #0x60]
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ldp x14, x15, [sp, #0x70]
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ldp x16, x17, [sp, #0x80]
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ldp x18, x30, [sp, #0x90]
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add sp, sp, SCRATCH_REG_SIZE
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.endm
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/* ----------------------------------------------------
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* Common TSP interrupt handling routine
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* ----------------------------------------------------
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*/
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.macro handle_tsp_interrupt label
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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save_caller_regs_and_lr
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bl tsp_common_int_handler
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cbz x0, interrupt_exit_\label
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/*
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* This interrupt was not targetted to S-EL1 so send it to
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* the monitor and wait for execution to resume.
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*/
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smc #0
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interrupt_exit_\label:
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restore_caller_regs_and_lr
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eret
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.endm
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.globl tsp_exceptions
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/* -----------------------------------------------------
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* TSP exception handlers.
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* -----------------------------------------------------
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*/
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vector_base tsp_exceptions
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/* -----------------------------------------------------
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* Current EL with _sp_el0 : 0x0 - 0x200. No exceptions
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* are expected and treated as irrecoverable errors.
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_sp_el0
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b plat_panic_handler
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end_vector_entry sync_exception_sp_el0
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vector_entry irq_sp_el0
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b plat_panic_handler
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end_vector_entry irq_sp_el0
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vector_entry fiq_sp_el0
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b plat_panic_handler
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end_vector_entry fiq_sp_el0
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vector_entry serror_sp_el0
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b plat_panic_handler
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end_vector_entry serror_sp_el0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs
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* are expected and handled
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_sp_elx
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b plat_panic_handler
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end_vector_entry sync_exception_sp_elx
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vector_entry irq_sp_elx
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handle_tsp_interrupt irq_sp_elx
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end_vector_entry irq_sp_elx
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vector_entry fiq_sp_elx
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handle_tsp_interrupt fiq_sp_elx
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end_vector_entry fiq_sp_elx
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vector_entry serror_sp_elx
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b plat_panic_handler
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end_vector_entry serror_sp_elx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600. No exceptions
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* are handled since TSP does not implement a lower EL
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_aarch64
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b plat_panic_handler
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end_vector_entry sync_exception_aarch64
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vector_entry irq_aarch64
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b plat_panic_handler
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end_vector_entry irq_aarch64
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vector_entry fiq_aarch64
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b plat_panic_handler
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end_vector_entry fiq_aarch64
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vector_entry serror_aarch64
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b plat_panic_handler
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end_vector_entry serror_aarch64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800. No exceptions
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* handled since the TSP does not implement a lower EL.
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* -----------------------------------------------------
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*/
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vector_entry sync_exception_aarch32
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b plat_panic_handler
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end_vector_entry sync_exception_aarch32
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vector_entry irq_aarch32
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b plat_panic_handler
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end_vector_entry irq_aarch32
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vector_entry fiq_aarch32
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b plat_panic_handler
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end_vector_entry fiq_aarch32
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vector_entry serror_aarch32
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b plat_panic_handler
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end_vector_entry serror_aarch32
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