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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
327 lines
9.1 KiB
ArmAsm
327 lines
9.1 KiB
ArmAsm
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/runtime_svc.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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#include <smccc_helpers.h>
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#include <smccc_macros.S>
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.globl sp_min_vector_table
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.globl sp_min_entrypoint
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.globl sp_min_warm_entrypoint
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.globl sp_min_handle_smc
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.globl sp_min_handle_fiq
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.macro route_fiq_to_sp_min reg
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/* -----------------------------------------------------
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* FIQs are secure interrupts trapped by Monitor and non
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* secure is not allowed to mask the FIQs.
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* -----------------------------------------------------
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*/
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ldcopr \reg, SCR
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orr \reg, \reg, #SCR_FIQ_BIT
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bic \reg, \reg, #SCR_FW_BIT
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stcopr \reg, SCR
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.endm
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.macro clrex_on_monitor_entry
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#if (ARM_ARCH_MAJOR == 7)
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/*
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* ARMv7 architectures need to clear the exclusive access when
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* entering Monitor mode.
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*/
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clrex
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#endif
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.endm
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vector_base sp_min_vector_table
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b sp_min_entrypoint
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b plat_panic_handler /* Undef */
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b sp_min_handle_smc /* Syscall */
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b plat_panic_handler /* Prefetch abort */
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b plat_panic_handler /* Data abort */
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b plat_panic_handler /* Reserved */
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b plat_panic_handler /* IRQ */
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b sp_min_handle_fiq /* FIQ */
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/*
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* The Cold boot/Reset entrypoint for SP_MIN
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*/
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func sp_min_entrypoint
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#if !RESET_TO_SP_MIN
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/* ---------------------------------------------------------------
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* Preceding bootloader has populated r0 with a pointer to a
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* 'bl_params_t' structure & r1 with a pointer to platform
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* specific structure
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* ---------------------------------------------------------------
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*/
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mov r9, r0
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mov r10, r1
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mov r11, r2
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mov r12, r3
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/* ---------------------------------------------------------------------
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* For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches
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* sp_min_entrypoint() during the cold boot flow, so the cold/warm boot
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* and primary/secondary CPU logic should not be executed in this case.
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*
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* Also, assume that the previous bootloader has already initialised the
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* SCTLR, including the CPU endianness, and has initialised the memory.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=0 \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=1 \
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_exception_vectors=sp_min_vector_table
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/* ---------------------------------------------------------------------
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* Relay the previous bootloader's arguments to the platform layer
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* ---------------------------------------------------------------------
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*/
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#else
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/* ---------------------------------------------------------------------
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* For RESET_TO_SP_MIN systems which have a programmable reset address,
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* sp_min_entrypoint() is executed only on the cold boot path so we can
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* skip the warm boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=sp_min_vector_table
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/* ---------------------------------------------------------------------
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* For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
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* to run so there's no argument to relay from a previous bootloader.
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* Zero the arguments passed to the platform layer to reflect that.
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* ---------------------------------------------------------------------
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*/
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mov r9, #0
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mov r10, #0
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mov r11, #0
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mov r12, #0
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#endif /* RESET_TO_SP_MIN */
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#if SP_MIN_WITH_SECURE_FIQ
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route_fiq_to_sp_min r4
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#endif
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mov r0, r9
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mov r1, r10
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mov r2, r11
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mov r3, r12
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bl sp_min_early_platform_setup2
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bl sp_min_plat_arch_setup
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/* Jump to the main function */
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bl sp_min_main
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/* -------------------------------------------------------------
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* Clean the .data & .bss sections to main memory. This ensures
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* that any global data which was initialised by the primary CPU
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* is visible to secondary CPUs before they enable their data
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* caches and participate in coherency.
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* -------------------------------------------------------------
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*/
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ldr r0, =__DATA_START__
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ldr r1, =__DATA_END__
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sub r1, r1, r0
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bl clean_dcache_range
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ldr r0, =__BSS_START__
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ldr r1, =__BSS_END__
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sub r1, r1, r0
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bl clean_dcache_range
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bl smc_get_next_ctx
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/* r0 points to `smc_ctx_t` */
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/* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
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b sp_min_exit
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endfunc sp_min_entrypoint
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/*
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* SMC handling function for SP_MIN.
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*/
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func sp_min_handle_smc
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/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
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str lr, [sp, #SMC_CTX_LR_MON]
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smccc_save_gp_mode_regs
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clrex_on_monitor_entry
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/*
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* `sp` still points to `smc_ctx_t`. Save it to a register
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* and restore the C runtime stack pointer to `sp`.
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*/
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mov r2, sp /* handle */
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ldr sp, [r2, #SMC_CTX_SP_MON]
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ldr r0, [r2, #SMC_CTX_SCR]
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and r3, r0, #SCR_NS_BIT /* flags */
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/* Switch to Secure Mode*/
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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/*
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* Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
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* Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
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* and so set to 1 as ARM has deprecated use of PMCR.LC=0.
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*/
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ldcopr r0, PMCR
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orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT)
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stcopr r0, PMCR
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ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */
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/* Check whether an SMC64 is issued */
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tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT)
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beq 1f
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/* SMC32 is not detected. Return error back to caller */
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mov r0, #SMC_UNK
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str r0, [r2, #SMC_CTX_GPREG_R0]
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mov r0, r2
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b sp_min_exit
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1:
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/* SMC32 is detected */
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mov r1, #0 /* cookie */
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bl handle_runtime_svc
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/* `r0` points to `smc_ctx_t` */
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b sp_min_exit
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endfunc sp_min_handle_smc
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/*
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* Secure Interrupts handling function for SP_MIN.
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*/
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func sp_min_handle_fiq
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#if !SP_MIN_WITH_SECURE_FIQ
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b plat_panic_handler
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#else
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/* FIQ has a +4 offset for lr compared to preferred return address */
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sub lr, lr, #4
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/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
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str lr, [sp, #SMC_CTX_LR_MON]
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smccc_save_gp_mode_regs
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clrex_on_monitor_entry
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/* load run-time stack */
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mov r2, sp
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ldr sp, [r2, #SMC_CTX_SP_MON]
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/* Switch to Secure Mode */
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ldr r0, [r2, #SMC_CTX_SCR]
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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/*
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* Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
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* Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
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* and so set to 1 as ARM has deprecated use of PMCR.LC=0.
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*/
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ldcopr r0, PMCR
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orr r0, r0, #(PMCR_LC_BIT | PMCR_DP_BIT)
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stcopr r0, PMCR
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push {r2, r3}
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bl sp_min_fiq
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pop {r0, r3}
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b sp_min_exit
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#endif
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endfunc sp_min_handle_fiq
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/*
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* The Warm boot entrypoint for SP_MIN.
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*/
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func sp_min_warm_entrypoint
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/*
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* On the warm boot path, most of the EL3 initialisations performed by
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* 'el3_entrypoint_common' must be skipped:
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*
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* - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by
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* programming the reset address do we need to initialied the SCTLR.
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* In other cases, we assume this has been taken care by the
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* entrypoint code.
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*
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* - No need to determine the type of boot, we know it is a warm boot.
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*
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* - Do not try to distinguish between primary and secondary CPUs, this
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* notion only exists for a cold boot.
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*
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* - No need to initialise the memory or the C runtime environment,
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* it has been done once and for all on the cold boot path.
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*/
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el3_entrypoint_common \
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_init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=0 \
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_exception_vectors=sp_min_vector_table
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/*
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* We're about to enable MMU and participate in PSCI state coordination.
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*
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* The PSCI implementation invokes platform routines that enable CPUs to
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* participate in coherency. On a system where CPUs are not
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* cache-coherent without appropriate platform specific programming,
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* having caches enabled until such time might lead to coherency issues
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* (resulting from stale data getting speculatively fetched, among
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* others). Therefore we keep data caches disabled even after enabling
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* the MMU for such platforms.
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*
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* On systems with hardware-assisted coherency, or on single cluster
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* platforms, such platform specific programming is not required to
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* enter coherency (as CPUs already are); and there's no reason to have
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* caches disabled either.
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*/
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#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
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mov r0, #0
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#else
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mov r0, #DISABLE_DCACHE
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#endif
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bl bl32_plat_enable_mmu
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#if SP_MIN_WITH_SECURE_FIQ
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route_fiq_to_sp_min r0
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#endif
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bl sp_min_warm_boot
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bl smc_get_next_ctx
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/* r0 points to `smc_ctx_t` */
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/* The PSCI cpu_context registers have been copied to `smc_ctx_t` */
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b sp_min_exit
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endfunc sp_min_warm_entrypoint
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/*
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* The function to restore the registers from SMC context and return
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* to the mode restored to SPSR.
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*
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* Arguments : r0 must point to the SMC context to restore from.
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*/
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func sp_min_exit
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monitor_exit
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endfunc sp_min_exit
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