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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
215 lines
6.8 KiB
ArmAsm
215 lines
6.8 KiB
ArmAsm
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <arch.h>
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#include <common/bl_common.h>
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#include <el3_common_macros.S>
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#include <lib/pmf/pmf_asm_macros.S>
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#include <lib/runtime_instr.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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.globl bl31_entrypoint
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.globl bl31_warm_entrypoint
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/* -----------------------------------------------------
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* bl31_entrypoint() is the cold boot entrypoint,
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* executed only by the primary cpu.
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* -----------------------------------------------------
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*/
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func bl31_entrypoint
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#if !RESET_TO_BL31
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/* ---------------------------------------------------------------
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* Stash the previous bootloader arguments x0 - x3 for later use.
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* ---------------------------------------------------------------
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*/
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mov x20, x0
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mov x21, x1
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mov x22, x2
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mov x23, x3
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/* ---------------------------------------------------------------------
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* For !RESET_TO_BL31 systems, only the primary CPU ever reaches
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* bl31_entrypoint() during the cold boot flow, so the cold/warm boot
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* and primary/secondary CPU logic should not be executed in this case.
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*
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* Also, assume that the previous bootloader has already initialised the
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* SCTLR_EL3, including the endianness, and has initialised the memory.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=0 \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=1 \
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_exception_vectors=runtime_exceptions
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#else
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/* ---------------------------------------------------------------------
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* For RESET_TO_BL31 systems which have a programmable reset address,
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* bl31_entrypoint() is executed only on the cold boot path so we can
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* skip the warm boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=runtime_exceptions
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/* ---------------------------------------------------------------------
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* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
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* there's no argument to relay from a previous bootloader. Zero the
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* arguments passed to the platform layer to reflect that.
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* ---------------------------------------------------------------------
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*/
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mov x20, 0
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mov x21, 0
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mov x22, 0
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mov x23, 0
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#endif /* RESET_TO_BL31 */
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/* --------------------------------------------------------------------
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* If PIE is enabled, fixup the Global descriptor Table and dynamic
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* relocations
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* --------------------------------------------------------------------
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*/
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#if ENABLE_PIE
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mov_imm x0, BL31_BASE
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mov_imm x1, BL31_LIMIT
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bl fixup_gdt_reloc
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#endif /* ENABLE_PIE */
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/* ---------------------------------------------
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* Perform platform specific early arch. setup
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* ---------------------------------------------
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*/
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mov x0, x20
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mov x1, x21
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mov x2, x22
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mov x3, x23
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bl bl31_early_platform_setup2
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bl bl31_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl31_main
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/* -------------------------------------------------------------
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* Clean the .data & .bss sections to main memory. This ensures
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* that any global data which was initialised by the primary CPU
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* is visible to secondary CPUs before they enable their data
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* caches and participate in coherency.
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* -------------------------------------------------------------
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*/
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adr x0, __DATA_START__
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adr x1, __DATA_END__
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sub x1, x1, x0
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bl clean_dcache_range
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adr x0, __BSS_START__
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adr x1, __BSS_END__
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sub x1, x1, x0
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bl clean_dcache_range
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b el3_exit
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endfunc bl31_entrypoint
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/* --------------------------------------------------------------------
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* This CPU has been physically powered up. It is either resuming from
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* suspend or has simply been turned on. In both cases, call the BL31
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* warmboot entrypoint
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* --------------------------------------------------------------------
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*/
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func bl31_warm_entrypoint
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#if ENABLE_RUNTIME_INSTRUMENTATION
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/*
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* This timestamp update happens with cache off. The next
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* timestamp collection will need to do cache maintenance prior
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* to timestamp update.
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*/
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pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_HW_LOW_PWR
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mrs x1, cntpct_el0
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str x1, [x0]
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#endif
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/*
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* On the warm boot path, most of the EL3 initialisations performed by
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* 'el3_entrypoint_common' must be skipped:
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*
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* - Only when the platform bypasses the BL1/BL31 entrypoint by
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* programming the reset address do we need to initialise SCTLR_EL3.
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* In other cases, we assume this has been taken care by the
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* entrypoint code.
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*
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* - No need to determine the type of boot, we know it is a warm boot.
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*
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* - Do not try to distinguish between primary and secondary CPUs, this
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* notion only exists for a cold boot.
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*
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* - No need to initialise the memory or the C runtime environment,
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* it has been done once and for all on the cold boot path.
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*/
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el3_entrypoint_common \
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_init_sctlr=PROGRAMMABLE_RESET_ADDRESS \
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_warm_boot_mailbox=0 \
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_secondary_cold_boot=0 \
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_init_memory=0 \
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_init_c_runtime=0 \
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_exception_vectors=runtime_exceptions
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/*
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* We're about to enable MMU and participate in PSCI state coordination.
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*
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* The PSCI implementation invokes platform routines that enable CPUs to
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* participate in coherency. On a system where CPUs are not
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* cache-coherent without appropriate platform specific programming,
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* having caches enabled until such time might lead to coherency issues
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* (resulting from stale data getting speculatively fetched, among
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* others). Therefore we keep data caches disabled even after enabling
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* the MMU for such platforms.
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*
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* On systems with hardware-assisted coherency, or on single cluster
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* platforms, such platform specific programming is not required to
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* enter coherency (as CPUs already are); and there's no reason to have
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* caches disabled either.
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*/
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#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
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mov x0, xzr
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#else
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mov x0, #DISABLE_DCACHE
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#endif
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bl bl31_plat_enable_mmu
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bl psci_warmboot_entrypoint
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#if ENABLE_RUNTIME_INSTRUMENTATION
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pmf_calc_timestamp_addr rt_instr_svc, RT_INSTR_EXIT_PSCI
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mov x19, x0
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/*
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* Invalidate before updating timestamp to ensure previous timestamp
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* updates on the same cache line with caches disabled are properly
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* seen by the same core. Without the cache invalidate, the core might
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* write into a stale cache line.
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*/
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mov x1, #PMF_TS_SIZE
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mov x20, x30
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bl inv_dcache_range
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mov x30, x20
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mrs x0, cntpct_el0
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str x0, [x19]
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#endif
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b el3_exit
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endfunc bl31_warm_entrypoint
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