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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
88 lines
2.1 KiB
ArmAsm
88 lines
2.1 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <el3_common_macros.S>
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.globl bl2_entrypoint
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.globl bl2_run_next_image
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func bl2_entrypoint
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/* Save arguments x0-x3 from previous Boot loader */
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mov r9, r0
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mov r10, r1
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mov r11, r2
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mov r12, r3
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl2_vector_table
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/*
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* Restore parameters of boot rom
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*/
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mov r0, r9
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mov r1, r10
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mov r2, r11
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mov r3, r12
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bl bl2_el3_early_platform_setup
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bl bl2_el3_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2_entrypoint
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func bl2_run_next_image
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mov r8,r0
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/*
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* MMU needs to be disabled because both BL2 and BL32 execute
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* in PL1, and therefore share the same address space.
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* BL32 will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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mov r0, r8
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bl bl2_el3_plat_prepare_exit
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/*
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* Extract PC and SPSR based on struct `entry_point_info_t`
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* and load it in LR and SPSR registers respectively.
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*/
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ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
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ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
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msr spsr, r1
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/* Some BL32 stages expect lr_svc to provide the BL33 entry address */
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cps #MODE32_svc
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ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
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cps #MODE32_mon
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add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
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ldm r8, {r0, r1, r2, r3}
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eret
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endfunc bl2_run_next_image
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