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09d40e0e08
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a2 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
157 lines
3.7 KiB
ArmAsm
157 lines
3.7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <context.h>
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#include <lib/xlat_tables/xlat_tables.h>
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#include <smccc_helpers.h>
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#include <smccc_macros.S>
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.globl bl1_aarch32_smc_handler
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func bl1_aarch32_smc_handler
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/* On SMC entry, `sp` points to `smc_ctx_t`. Save `lr`. */
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str lr, [sp, #SMC_CTX_LR_MON]
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/* ------------------------------------------------
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* SMC in BL1 is handled assuming that the MMU is
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* turned off by BL2.
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* ------------------------------------------------
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*/
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/* ----------------------------------------------
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* Detect if this is a RUN_IMAGE or other SMC.
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* ----------------------------------------------
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*/
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mov lr, #BL1_SMC_RUN_IMAGE
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cmp lr, r0
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bne smc_handler
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/* ------------------------------------------------
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* Make sure only Secure world reaches here.
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* ------------------------------------------------
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*/
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ldcopr r8, SCR
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tst r8, #SCR_NS_BIT
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blne report_exception
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/* ---------------------------------------------------------------------
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* Pass control to next secure image.
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* Here it expects r1 to contain the address of a entry_point_info_t
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* structure describing the BL entrypoint.
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* ---------------------------------------------------------------------
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*/
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mov r8, r1
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mov r0, r1
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bl bl1_print_next_bl_ep_info
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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debug_loop:
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b debug_loop
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#endif
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mov r0, r8
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bl bl1_plat_prepare_exit
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stcopr r0, TLBIALL
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dsb sy
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isb
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/*
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* Extract PC and SPSR based on struct `entry_point_info_t`
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* and load it in LR and SPSR registers respectively.
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*/
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ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
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ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
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msr spsr, r1
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/* Some BL32 stages expect lr_svc to provide the BL33 entry address */
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cps #MODE32_svc
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ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET]
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cps #MODE32_mon
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add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
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ldm r8, {r0, r1, r2, r3}
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eret
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endfunc bl1_aarch32_smc_handler
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/* -----------------------------------------------------
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* Save Secure/Normal world context and jump to
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* BL1 SMC handler.
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* -----------------------------------------------------
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*/
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func smc_handler
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/* -----------------------------------------------------
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* Save the GP registers.
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* -----------------------------------------------------
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*/
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smccc_save_gp_mode_regs
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/*
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* `sp` still points to `smc_ctx_t`. Save it to a register
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* and restore the C runtime stack pointer to `sp`.
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*/
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mov r6, sp
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ldr sp, [r6, #SMC_CTX_SP_MON]
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ldr r0, [r6, #SMC_CTX_SCR]
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and r7, r0, #SCR_NS_BIT /* flags */
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/* Switch to Secure Mode */
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bic r0, #SCR_NS_BIT
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stcopr r0, SCR
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isb
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/* If caller is from Secure world then turn on the MMU */
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tst r7, #SCR_NS_BIT
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bne skip_mmu_on
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/* Turn on the MMU */
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mov r0, #DISABLE_DCACHE
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bl enable_mmu_svc_mon
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/* Enable the data cache. */
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ldcopr r9, SCTLR
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orr r9, r9, #SCTLR_C_BIT
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stcopr r9, SCTLR
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isb
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skip_mmu_on:
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/* Prepare arguments for BL1 SMC wrapper. */
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ldr r0, [r6, #SMC_CTX_GPREG_R0] /* smc_fid */
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mov r1, #0 /* cookie */
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mov r2, r6 /* handle */
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mov r3, r7 /* flags */
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bl bl1_smc_wrapper
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/* Get the smc_context for next BL image */
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bl smc_get_next_ctx
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mov r4, r0
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/* Only turn-off MMU if going to secure world */
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ldr r5, [r4, #SMC_CTX_SCR]
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tst r5, #SCR_NS_BIT
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bne skip_mmu_off
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/* Disable the MMU */
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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skip_mmu_off:
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/* -----------------------------------------------------
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* Do the transition to next BL image.
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* -----------------------------------------------------
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*/
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mov r0, r4
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monitor_exit
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endfunc smc_handler
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