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04c7303b9c
When a core is in debug recovery mode its caches are not invalidated upon reset, so the L1 and L2 cache contents from before reset are observable after reset. Similarly, debug recovery mode of DynamIQ cluster ensures that contents of the shared L3 cache are also not invalidated upon transition to On mode. Booting cores in debug recovery mode means booting with caches disabled and preserving the caches until a point where software can dump the caches and retrieve their contents. TF-A however unconditionally cleans and invalidates caches at multiple points during boot. This can lead to memory corruption as well as loss of cache contents to be used for debugging. This patch fixes this by calling a platform hook before performing CMOs in helper routines in cache_helpers.S. The platform hook plat_can_cmo is an assembly routine which must not clobber x2 and x3, and avoid using stack. The whole checking is conditional upon `CONDITIONAL_CMO` which can be set at compile time. Signed-off-by: Okash Khawaja <okash@google.com> Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193
255 lines
7 KiB
ArmAsm
255 lines
7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl flush_dcache_range
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.globl clean_dcache_range
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.globl inv_dcache_range
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.globl dcsw_op_louis
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.globl dcsw_op_all
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.globl dcsw_op_level1
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.globl dcsw_op_level2
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.globl dcsw_op_level3
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/*
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* This macro can be used for implementing various data cache operations `op`
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*/
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.macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2
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/* Exit early if size is zero */
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cmp r1, #0
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beq exit_loop_\op
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dcache_line_size r2, r3
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add r1, r0, r1
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sub r3, r2, #1
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bic r0, r0, r3
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loop_\op:
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stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
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add r0, r0, r2
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cmp r0, r1
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blo loop_\op
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dsb sy
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exit_loop_\op:
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bx lr
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.endm
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.macro check_plat_can_cmo
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#if CONDITIONAL_CMO
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mov r3, lr
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mov r2, r0
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bl plat_can_cmo
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mov lr, r3
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cmp r0, #0
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bne 1f
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bx lr
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1:
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mov r0, r2
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#endif
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.endm
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/* ------------------------------------------
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* Clean+Invalidate from base address till
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* size. 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func flush_dcache_range
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check_plat_can_cmo
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do_dcache_maintenance_by_mva cimvac, DCCIMVAC
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endfunc flush_dcache_range
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/* ------------------------------------------
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* Clean from base address till size.
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* 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func clean_dcache_range
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check_plat_can_cmo
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do_dcache_maintenance_by_mva cmvac, DCCMVAC
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endfunc clean_dcache_range
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/* ------------------------------------------
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* Invalidate from base address till
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* size. 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func inv_dcache_range
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check_plat_can_cmo
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do_dcache_maintenance_by_mva imvac, DCIMVAC
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endfunc inv_dcache_range
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/* ----------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* r1: The cache level to begin operation from
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* r2: clidr_el1
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* r3: The last cache level to operate on
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* and will carry out the operation on each data cache from level 0
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* to the level in r3 in sequence
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*
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* The dcsw_op macro sets up the r2 and r3 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ----------------------------------------------------------------
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*/
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.macro dcsw_op shift, fw, ls
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ldcopr r2, CLIDR
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ubfx r3, r2, \shift, \fw
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lsl r3, r3, \ls
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mov r1, #0
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b do_dcsw_op
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.endm
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func do_dcsw_op
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push {r4-r12, lr}
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ldcopr r8, ID_MMFR4 // stash FEAT_CCIDX identifier in r8
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ubfx r8, r8, #ID_MMFR4_CCIDX_SHIFT, #ID_MMFR4_CCIDX_LENGTH
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adr r11, dcsw_loop_table // compute cache op based on the operation type
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add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions
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loop1:
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add r10, r1, r1, LSR #1 // Work out 3x current cache level
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mov r12, r2, LSR r10 // extract cache type bits from clidr
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and r12, r12, #7 // mask the bits for current cache only
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cmp r12, #2 // see what cache we have at this level
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blo level_done // no cache or only instruction cache at this level
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stcopr r1, CSSELR // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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ldcopr r12, CCSIDR // read the new ccsidr
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and r10, r12, #7 // extract the length of the cache lines
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add r10, r10, #4 // add 4 (r10 = line length offset)
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cmp r8, #0 // check for FEAT_CCIDX for Associativity
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beq 1f
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ubfx r4, r12, #3, #21 // r4 = associativity CCSIDR[23:3]
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b 2f
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1:
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ubfx r4, r12, #3, #10 // r4 = associativity CCSIDR[12:3]
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2:
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clz r5, r4 // r5 = the bit position of the way size increment
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mov r9, r4 // r9 working copy of the aligned max way number
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loop2:
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cmp r8, #0 // check for FEAT_CCIDX for NumSets
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beq 3f
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ldcopr r12, CCSIDR2 // FEAT_CCIDX numsets is in CCSIDR2
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ubfx r7, r12, #0, #24 // r7 = numsets CCSIDR2[23:0]
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b loop3
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3:
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ubfx r7, r12, #13, #15 // r7 = numsets CCSIDR[27:13]
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loop3:
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orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
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orr r0, r0, r7, LSL r10 // factor in the set number
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blx r6
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subs r7, r7, #1 // decrement the set number
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bhs loop3
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subs r9, r9, #1 // decrement the way number
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bhs loop2
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level_done:
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add r1, r1, #2 // increment the cache number
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cmp r3, r1
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// Ensure completion of previous cache maintenance instruction. Note
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// this also mitigates erratum 814220 on Cortex-A7
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dsb sy
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bhi loop1
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mov r6, #0
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stcopr r6, CSSELR //select cache level 0 in csselr
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dsb sy
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isb
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pop {r4-r12, pc}
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dcsw_loop_table:
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stcopr r0, DCISW
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bx lr
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stcopr r0, DCCISW
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bx lr
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stcopr r0, DCCSW
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bx lr
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endfunc do_dcsw_op
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/* ---------------------------------------------------------------
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* Data cache operations by set/way till PoU.
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*
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* The function requires :
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_louis
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check_plat_can_cmo
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dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_louis
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/* ---------------------------------------------------------------
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* Data cache operations by set/way till PoC.
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*
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* The function requires :
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_all
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check_plat_can_cmo
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_all
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/* ---------------------------------------------------------------
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* Helper macro for data cache operations by set/way for the
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* level specified
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op_level level
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ldcopr r2, CLIDR
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mov r3, \level
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sub r1, r3, #2
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b do_dcsw_op
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.endm
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 1 cache
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level1
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check_plat_can_cmo
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dcsw_op_level #(1 << LEVEL_SHIFT)
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endfunc dcsw_op_level1
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 2 cache
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level2
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check_plat_can_cmo
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dcsw_op_level #(2 << LEVEL_SHIFT)
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endfunc dcsw_op_level2
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 3 cache
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level3
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check_plat_can_cmo
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dcsw_op_level #(3 << LEVEL_SHIFT)
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endfunc dcsw_op_level3
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