3 commits

Author	SHA1	Message	Date
Sieu Mun Tang	b3d2850842	fix(intel): update Agilex5 BL2 init flow and other misc changes ... BL2: Update BL2 init flow, Timer base address, avoid cache flush of BL2 image descriptors BL31: Remove re-init of CCU and other misc updates Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>	2024-10-09 20:04:16 +02:00
Hadi Asyrafi	32cf34acac	intel: Implement platform specific system reset 2 ... Add support for platform specific warm-reset through psci system reset 2. - system_reset2 implementation that calls for l2 cache reset - Check for magic number and request for warm reset in bl2 - Create a shared reset manager header file for Agilex and Stratix 10 - Clean up parameter info in plat_get_next_bl_params Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3fdd9a2711c80d9bd3dc05b81527781d840bd726	2019-12-30 10:17:04 +08:00
Hadi Asyrafi	d8820789ca	intel: Platform common code refactor ... Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc	2019-08-01 16:39:27 +08:00

Renamed from plat/intel/soc/agilex/socfpga_image_load.c (Browse further)