Commit graph

8 commits

Author SHA1 Message Date
Harrison Mutai
df960bcc3b refactor(arm): replace hard-coded HW_CONFIG DT size
Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2024-04-12 06:28:33 +00:00
Tamas Ban
48d42ed5a4 refactor(morello): update SDS driver calls
Update SDS driver calls to align with recent
changes [1] of the SDS driver.

- The driver now requires us to explicitly pass
  the SDS region id to act on.
- Implement plat_sds_get_regions() platform function
  which is used by the driver to get SDS region
  information per platform.

[1]: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/24609/

Change-Id: I942599edb4d9734c0455f67c6b5673aace62e444
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
2024-02-13 14:36:14 +01:00
Werner Lewis
80f8769b26 fix(morello): configure platform specific secure SPIs
Previous implementation used common CSS interrupts, which do not match
the Morello platform interrupt map. Updated to configure Secure
interrupts according to the Morello TRM and InfraSYSDESIGN4.0
specification.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I783a472d92601d86f1844f0d035dd0d036b2bfca
2023-06-22 22:36:57 +02:00
Chandni Cherukuri
cc266bcd8c feat(morello): implement methods to retrieve soc-id information
Added silicon revision in the platform information SDS structure.

Implemented platform functions to retrieve the soc-id information
for the morello SoC platform. SoC revision, which is same as
silicon revision, is fetched from the morello_plat_info structure
and SoC version is populated with the part number from SSC_VERSION
register, and is reflected in bits[0:15] of soc-id.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I8e0c5b2bc21e393e6d638858cc2ea9f4638f04b9
2023-03-15 10:33:08 +05:30
Chandni Cherukuri
07302a23ec fix(morello): change the AP runtime UART address
SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: Iecefb0d2cb875b3ecf97e0983b06f6e914835021
2021-12-16 19:56:31 +05:30
Manoj Kumar
4af5397753 feat(morello): add changes to enable TBBR boot
This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c
2021-12-16 19:55:08 +05:30
Chandni Cherukuri
6c07a9273b morello: Add changes to fix build of Morello Platform
This patch makes changes required to get the morello
platform working with the tip of TF-A.

Change-Id: I095006615c9959bba49fcc75b52e1de7d7486309
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
2020-10-02 12:25:09 +05:30
Chandni Cherukuri
dfd5bfb097 plat/arm: Add platform support for Morello
This patch adds support for Morello platform.
It is an initial port which includes only BL31 support
as the System Control Processor (SCP) is expected to take
the role of primary bootloader.

Change-Id: I1ecbe5a14a2d487b2ecea3c1ca227f08473ed2dd
Co-authored-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: Anurag Koul <anurag.koul@arm.com>
2020-09-28 19:33:24 +05:30