The UUID field in SP manifest DTS is represented as an array of four
integers that the SPMC consumes using the little endian representation.
The reason is that those values are directly mapped to the SMCCC section
5.3 recommendation and the way they are exposed to the
FFA_PARTITION_INFO_GET interface.
Per [1] TF-A build flow expects a big endian representation of the UUID
so the sp_mk_generator script is updated to accommodate this conversion.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9563
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I7c7b295225e23ea64f49170e27d97442b289703b
* changes:
feat(docs/nxp/layerscape): add ls1028a soc and board support
feat(plat/nxp/ls1028ardb): add ls1028ardb board support
feat(plat/nxp/ls1028a): add ls1028a soc support
feat(plat/nxp/common): define default SD buffer
feat(driver/nxp/xspi): add MT35XU02G flash info
feat(plat/nxp/common): add SecMon register definition for ch_3_2
feat(driver/nxp/dcfg): define RSTCR_RESET_REQ
feat(plat/nxp/common/psci): define CPUECTLR_TIMER_2TICKS
feat(plat/nxp/common): define default PSCI features if not defined
feat(plat/nxp/common): define common macro for ARM registers
feat(plat/nxp/common): add CCI and EPU address definition
The LS1028A reference design board (RDB) is a computing,
evaluation, and development platform that supports industrial
IoT applications, human machine interface solutions, and
industrial networking.
It supports the following features:
1. Layerscape LS1028A dual-core processor based on Cortex-A72
at 1.3 GHz.
2. 4 GB DDR4 SDRAM w/ECC
3. Support Ethernet:
1) x1 RJ45 connector for 1Gbps Ethernet support w/TSN, 1588
2) x4 RJ45 connector for 1Gbps Ethernet switch support w/TSN,
1588 (QSGMII)
3. With Basic Peripherals and Interconnect
2x M.2 Type E slots with PCIe Gen 3.0 x1
1x M.2 Type B slot with SATA 3.0 (resistor mux with 1 Type E slot)
1x Type A USB 3.0 super-speed port
1x Type C USB 3.0 super-speed port
1x DisplayPort interface
2x DB9 RS232 serial ports
2x DB9 CAN interfaces
1x 3.5 mm audio out
2x MikroBUS™ sockets
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: York Sun <york.sun@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Change-Id: I48ee254a488ae4af227641da3875a1e9a63a720c
The QorIQ LS1028A processor integrates two 64-bit ARM Cortex-A72
cores with a GPU and LCD controller, as well as a TSNenabled
Ethernet port and a TSN-enabled switch with four external ports.
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Change-Id: I9f65c6af5db7e20702828cd208290c1b43a54941
* changes:
feat(plat/fvp): enable trace extension features by default
feat(trf): enable trace filter control register access from lower NS EL
feat(trf): initialize trap settings of trace filter control registers access
feat(sys_reg_trace): enable trace system registers access from lower NS ELs
feat(sys_reg_trace): initialize trap settings of trace system registers access
feat(trbe): enable access to trace buffer control registers from lower NS EL
feat(trbe): initialize trap settings of trace buffer control registers access
Trusted Services had removed secure storage and added two new
trusted services - Protected Storage and Internal Trusted Storage.
Hence we are removing secure storage and adding support for the
internal trusted storage.
And enable external SP images in BL2 config for TC, so that
we do not have to modify this file whenever the list of SPs
changes. It is already implemented for fvp in the below commit.
commit 33993a3737
Author: Balint Dobszay <balint.dobszay@arm.com>
Date: Fri Mar 26 15:19:11 2021 +0100
feat(fvp): enable external SP images in BL2 config
Change-Id: I3e0a0973df3644413ca5c3a32f36d44c8efd49c7
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
Disabling filter 0 causes inability to access DRAM.
An attempt leads to an abort.
ARM manual disallows to disable filter 0, but if we do
that from SRAM, nothing bad happens.
This patch prevents disabling of a filter 0, allowing to
reconfigure other filters from DRAM.
Note: this patch doesn't change the logic after reset.
It is only needed in case someone wants to reconfigure the
previously configured TZASC.
Change-Id: I196a0cb110a89afbde97f64a94df3101f28708a4
Signed-off-by: stsp@users.sourceforge.net
Define default SD buffer address and size in DRAM.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5872d95b0c1114e05f0e145756e9a6ef39b2fd9a
Define RSTCR_RESET_REQ for Chassis V3.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I5cb7019baae5fe0d06b3d5e65f185f87ee16ad3a
SoC code can define supported features, otherwise use default setting.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I0f11498c1f7558ff0ec2d9b344f3f7a4f5489ced
Define common register macro both for Cortex-A53 and Cortex-A72
because the code will be used by both Cortex platform.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I485661bfe3ed4f214c403ff6af53dc6af1ddf089
Add CCI and EPU base address definiton for Chassis v3.2.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I13250555b6646c1e7ba2e9d7c9efca8501f17b3a
EMI MPU stands for external memory interface memory protect unit.
MT8195 supports 32 regions and 16 domains.
We add basic drivers currently, and will add more setting for
EMI MPU in next patch.
Change-Id: Iedc19d8f6fcf1ceb2d8241319b8dc17c885642dd
Signed-off-by: Penny Jan <penny.jan@mediatek.com>
In the SCMI power domain off handling, configure GIC
to prevent interrupt toward to the core to be turned off,
and configure CCN to disable coherency when the cluster is turned off.
The same operation is done in SCPI power domain off processing.
This commit adds the missing operation in SCMI power domain
off handling.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781
This change refactors the SPMD to setup SPMC CPU contexts once and early
from spmd_spmc_init (single call to cm_setup_context rather than on each
and every warm boot).
Pass the core linear ID through a GP register as an implementation
defined behavior helping FF-A adoption to legacy TOSes (essentially
when secure virtualization is not used).
A first version of this change was originally submitted by Lukas [1].
Pasting below the original justification:
Our TEE, Kinibi, is used to receive the core linear ID in the x3
register of booting secondary cores.
This patch is necessary to bring up secondary cores with Kinibi as an
SPMC in SEL1.
In Kinibi, the TEE is mostly platform-independent and all platform-
specifics like topology is concentrated in TF-A of our customers.
That is why we don't have the MPIDR - linear ID mapping in Kinibi.
We need the correct linear ID to program the GICv2 target register,
for example in power management case.
It is not needed on GICv3/v4, because of using a fixed mapping from
MPIDR to ICDIPTR/GICD_ITARGETSRn register.
For debug and power management purpose, we also want a unified view to
linear id between Linux and the TEE.
E.g. to disable a core, to see what cores are printing a trace /
an event.
In the past, Kinibi had several other designs, but the complexity was
getting out of control:
* Platform-specific assembler macros in the kernel.
* A per-core SMC from Linux to tell the linear ID after the boot.
* With DynamiQ, it seems SIPs were playing with MPIDR register values,
reusing them between cores and changing them during boot.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/10235
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
Change-Id: Ifa8fa208e9b8eb1642c80b5f7b54152dadafa75e
This patch will fix the formatting errors concerning code snippet,
lines 245 and 256 respectively.
The code snippet is updated to 'shell' to lex it appropriately.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I53aefd81da350b6511e7a97b5fee7b0d6f9dde2d
Erratum 1530924 affects Armada 37xx CPU, since it affects all Cortex-A53
revisions from r0p0 to r0p4.
Enable the workaround for this erratum.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Change-Id: I753225040e49e956788d5617cd7ce76d5e6ea8e8
Describe the boot using FIP, and how to compile it.
The STM32IMAGE boot chain is still available but it is not recommended.
Update the build command lines, for FIP.
The memory mapping is also updated.
Change-Id: I2b1e0df5500b6213d33dc558b0e0da38340a4d79
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
