This fix is to flush and invalidate the caches before cold reset.
Issue happen where Agilex5 hardware does not support the caches flush.
Thus software workaround is needed.
Change-Id: Ibfeecbc611d238a069ca72f8b833f319e794cd38
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Update stream id to non-secure for SDM which is to
bring up FPGA config via SMMU.
Change-Id: Ib8836fa0cf31fe0cfc0261123e051772923bb66b
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
This patch is used to implement CCU driver for
Agilex5 SoC FPGA.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c00d9e050e60c883725
Incorrect value stored in Coherent Subsystem ACE DVM Snoop Enable
register (CSADSER0). Set individual bit othervise previous value
is overwritten.
Signed-off-by: Anders Hedlund <anders.hedlund@windriver.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ib72fed261cbc3076ce385e19c4a5fa8e9e8b9924
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I385455671413e154d04a879d33fdd774fcfefbd6
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb
Clear Ncore CCU snoop filter. There is hardware bug in NCORE CCU IP
and it is causing an issue in the coherent directory tracking of
outstanding cache lines.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9ee67c94e6379d318516ae8f660a62323ce8d563
Set OCRAM as secure region and required privileged access in BL31 to
prevent software running in normal world (non-secure) accessing memory
region in OCRAM which may contain sensitive information (e.g. FSBL,
handoff data)
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib6b24efd69f49cd3f9aa4ef2ea9f1af5ce582bd6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
This adds the ncore ccu access and enable access to the
on-chip ram for N5X device in BL31.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I713f6e93d33b6e91705547477ca32cfba5c8c13d
The CCU initialization loop uses the wrong units, this fixes that. This
also fixes snoop filter register set bits should be used instead of
overwriting the register
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia15eeeae5569b00ad84120182170d353ee221b31
