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2 commits

Author SHA1 Message Date
Sieu Mun Tang
b3d2850842 fix(intel): update Agilex5 BL2 init flow and other misc changes 
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
 2024-10-09 20:04:16 +02:00
Jit Loon Lim
a8bf898f02 feat(intel): power manager for Agilex5 SoC FPGA 
This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
	1. Added power manager support.
	2. Updated product name -> Agilex5

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3
 2023-07-05 09:08:47 +08:00