TF-A BL2 always boot at 650MHz using an algorithm to calculate PLL1
settings, without reading DT. Remove the corresponding nodes.
Change-Id: I0003337d8d37df7b2a70a84b5475f4278c4c4669
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
LSI was too slow to provide enough random numbers (limited
to 6ms for 16 bytes production). Switch to CSI that allow
to get the RNG fifo ready in less than 50µs.
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
Change-Id: I76d1fe58e2f4d5416a96f48123ae36bd82d8a8ee
This is something commonly asked by Linux kernel DT maintainers [1].
The mentioned doc is not upstreamed, but may be checked with dtbs_check.
While at it align some nodes with Linux or OP-TEE.
[1] https://lore.kernel.org/linux-arm-kernel/20231125184422.12315-1-krzysztof.kozlowski@linaro.org/
Change-Id: I63e983c2a00eda3cd8b81c66c0cd1a97cf8249b7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
The RCC security is managed with a dedicated compatible:
"st,stm32mp1-rcc-secure" [1].
Remove useless secure-status property in boards rcc nodes.
[1] 812daf916c ("feat(st): update the security based on new compatible")
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Iff31044ade78dd9c432120dce65375fe2b0d36d6
With recent changes, TF-A now panics on MC-1, Avenger96 and Odyssey:
NOTICE: CPU: STM32MP157C?? Rev.B
NOTICE: Model: Linux Automation MC-1 board
ERROR: regul ldo3: max value 750 is invalid
PANIC at PC : 0x2ffeebb7
as the driver takes great offense at the content of the device
tree. The parts in question were copy-pasted from ST DTs, but
those ST DTs were fixed by commit 67d95409ba
("refactor(stm32mp1-fdts): update regulator description").
Fix the breakage by transplanting the same changes into all
remaining STM32MP1 DTs.
Change was boot-tested on MC-1, but only build tested for the
other two.
Fixes: bba9fdee58 ("feat(stm32mp1): add regulator framework compilation")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Change-Id: I143d0091625f62c313b3b71449c9ad99583d01c8
The Linux Automation MC-1 is a SBC built around the Octavo Systems
OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
PMIC. The board has eMMC and a SD slot for storage.
The SDRAM calibration values are taken as is from the DKx boards, which
seem to be suitable for operation at German room temperature.
This is deemed ok for now, but for use in the field, the SiP will likely
need to have its timings determined in a climate chamber.
Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
