Commit graph

11690 commits

Author SHA1 Message Date
Tamas Ban
c201d6e8d1 docs: add threat model for AP-RSS interface
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ic818da12584503e1a96396c4b55a8db14ae7584a
2022-12-09 10:15:09 +01:00
Alexei Fedorov
a0f256b033 Merge "fix(rmmd): add missing padding to RMM Boot Manifest and initialize it" into integration 2022-12-08 14:53:50 +01:00
Sandrine Bailleux
cb875fd31a Merge "docs: extend generic tf-a threat model" into integration 2022-12-08 09:29:49 +01:00
Javier Almansa Sobrino
dc0ca64e4b fix(rmmd): add missing padding to RMM Boot Manifest and initialize it
This patch also:
     * Enforces the check of RES0 fields on EL3-RMM boot interface
       and manifest
     * Fixes a couple of nits on the EL3-RMM Boot Interface
       documentation.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: Idb9e38f9fcda2ba0655646a1e2c4fdbabd5cdc40
2022-12-07 18:54:28 +00:00
Sandrine Bailleux
825641d615 Merge changes Ida9abfd5,Iec447d97 into integration
* changes:
  build: enable adding MbedTLS files for platform
  feat(lib/psa): add read_measurement API
2022-12-07 13:51:57 +01:00
Soby Mathew
ca32548a3b Merge "fix(trp): preserve RMI SMC X4 when not used as return" into integration 2022-12-07 12:14:56 +01:00
AlexeiFedorov
b96253db08 fix(trp): preserve RMI SMC X4 when not used as return
This patch adds X2-X6 and 'smc_ret' parameters to trp_rmi_handler().
The last 'smc_ret' parameter passed in X7 contains address of
'trp_smc_result' structure on stack to return result of RMI SMC call.

This allows to preserve X4 if not used as a return argument as per
SMCCCv1.2. The patch also removes use of trp_args_t in RMI handling.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I9e3387a7380b37863eeccc53d13e92e0ac5cffbd
2022-12-07 13:12:30 +02:00
Soby Mathew
b8dbfacc44 Merge "feat(rmm): add support for the 2nd DRAM bank" into integration 2022-12-07 06:03:38 +01:00
Sandrine Bailleux
cd3a7794cb Merge "feat(intel): extending to support SMMU in FCS" into integration 2022-12-06 17:27:17 +01:00
Sandrine Bailleux
9ccdfc44af Merge "fix(intel): fix fcs_client crashed when increased param size" into integration 2022-12-06 17:27:07 +01:00
Sandrine Bailleux
34ffe4aaca Merge changes Ia8f1471a,I6b95c19d into integration
* changes:
  fix(intel): agilex bitstream pre-authenticate
  fix(intel): mailbox store QSPI ref clk in scratch reg
2022-12-06 17:26:22 +01:00
Sandrine Bailleux
936455eb08 Merge "fix(rss): do not consider MHU_ERR_ALREADY_INIT as error" into integration 2022-12-06 15:55:28 +01:00
AlexeiFedorov
346cfe2b46 feat(rmm): add support for the 2nd DRAM bank
This patch adds support for RMM granules allocation
in FVP 2nd DRAM 2GB bank at 0x880000000 base address.
For ENABLE_RME = 1 case it also removes "mem=1G"
Linux kernel command line option in fvp-base-psci-common.dsti
to allow memory layout discovery from the FVP device tree.
FVP parameter 'bp.dram_size' - size of main memory in gigabytes
documented in docs/components/realm-management-extension.rst
is changed from 2 to 4.

Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>
Change-Id: I174da4416ad5a8d41bf0ac89f356dba7c0cd3fe7
2022-12-06 12:29:43 +00:00
David Vincze
55a7aa9252 fix(rss): do not consider MHU_ERR_ALREADY_INIT as error
rss_comms_init() should return with success (0) in case of an internal
MHU_ERR_ALREADY_INIT error code which is harmless (occurs when
rss_comms_init() is called multiple times in a row).

Change-Id: Ibb1fef48a60866e80d3a389128cb8eef1332ea01
Signed-off-by: David Vincze <david.vincze@arm.com>
2022-12-06 12:05:02 +01:00
Manish Pandey
15b70939c7 Merge "feat(qemu): support pointer authentication" into integration 2022-12-06 10:19:40 +01:00
Sandrine Bailleux
0312769f09 Merge "refactor(arm): remove unused global" into integration 2022-12-06 09:55:23 +01:00
Jit Loon Lim
c42402cdf8 fix(intel): fix fcs_client crashed when increased param size
No overflow buffer checking for param size. There is a security threat.
Update code to check for param size according to cryto param mode.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I37a2d047edd9ff835b3f0986d85309c402887bef
2022-12-06 11:52:01 +08:00
Sieu Mun Tang
4687021d2e feat(intel): extending to support SMMU in FCS
This patch is to extend support SMMU in FCS GET_DIGEST, MAC_VERIFY,
ECDSA_SHA2_DATA_SIGNING and ECDSA_SHA2_DATA_SIGNATURE_VERIFY.
It also will change to use asynchronous mailbox send command to improve
fcs_client timing performance.
Increase the SIP_SVC_VERSION_MAJOR because SMMU support is not backward
compatible.
Increase the SIP_SVC_VERSION_MINOR because 8 news function IDs are
introduced.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I15e619e246531b065451f9b201646f3c50e26307
2022-12-06 10:55:17 +08:00
Manish V Badarkhe
d8359cfaf0 refactor(arm): remove unused global
Removed unused global from the assembly file.

Change-Id: I17ab70aa888af27865a9fb4436495197f460780f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-12-05 09:35:26 +00:00
Joanna Farley
10f4d1a2d0 Merge "fix(zynqmp): initialize uint32 with value 0U in pm code" into integration 2022-12-01 18:50:50 +01:00
Manish Pandey
5d2edf60c3 Merge "fix(el3_runtime): restore SPSR/ELR/SCR after esb" into integration 2022-12-01 16:31:19 +01:00
Tamas Ban
1fba1a8558 docs: extend generic tf-a threat model
Adding a new threat which is about leaving
sensitive information in internal buffers
which could be stolen by an attacker.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I737e802c0adc9b00c89a0e21779745c51afb4b17
2022-12-01 14:00:18 +01:00
Naman Patel
e65584a017 fix(zynqmp): initialize uint32 with value 0U in pm code
MISRA Violation: MISRA C-2012 Rule 7.2
- Initialize the unsigned int with value 0u in pm_service component.

Current misra warning detection tool is not reporting this as
warning. It reports only when the initialized value exceeds the
range of data type based on compiler used.

But, this change is added as a part of precaution as some other
misra checker tool may report it as violation of rule 7.2.

Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I50a5cee2a077fe157e79757d959ce33064225af3
2022-12-01 03:11:04 -08:00
Manish Pandey
2b9c8b877c Merge "build: restrict usage of CTX_INCLUDE_EL2_REGS" into integration 2022-12-01 11:08:07 +01:00
Govindraj Raja
f1910cc178 build: restrict usage of CTX_INCLUDE_EL2_REGS
CTX_INCLUDE_EL2_REGS is used to save/restore EL2 registers and
it should be only used when there is SPMD or RME enabled.

Make CTX_INCLUDE_EL2_REGS an internal macro and remove
from documentation.

Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I6a70edfd88163423ff0482de094601cf794246d6
2022-12-01 12:04:40 +02:00
Manish Pandey
ff1d2ef387 fix(el3_runtime): restore SPSR/ELR/SCR after esb
SCR_EL3 register is restored before esb issued and it is assumed
that EAs are unmasked at that point, which is wrong, as the SCR_EL3
value at that time is restored from the context of the world where
it is returning to.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Id1c7150a70b5f589b0dc7c50c359b4d23ee9f256
2022-12-01 10:26:42 +01:00
Manish Pandey
caaca4a104 Merge changes from topic "mb/refactor-evlog" into integration
* changes:
  refactor(qemu): pass platform metadata as a function's argument
  refactor(imx8m): pass platform metadata as a function's argument
  refactor(fvp): pass platform metadata as a function's argument
  refactor(measured-boot): accept metadata as a function's argument
2022-11-30 14:17:08 +01:00
Manish Pandey
c6432394a9 Merge "fix(console): fix crash on spin_unlock with cache disabled" into integration 2022-11-29 10:32:46 +01:00
Baruch Siach
5fb6946ad7 fix(console): fix crash on spin_unlock with cache disabled
Current code skips load of spinlock address when cache is disabled. The
following call to spin_unlock stores into the random location that x0
points to.

Move spinlock address load earlier so that x0 is always valid on
spin_unlock call.

Change-Id: Iac640289725dce2518f2fed483d7d36ca748ffe8
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2022-11-29 03:35:23 +01:00
Lauren Wehrmeister
d3d2a5a484 Merge "fix(cpus): workaround for Cortex-X3 erratum 2615812" into integration 2022-11-28 18:15:06 +01:00
Sandrine Bailleux
bf09c416ab Merge "fix(intel): fix print out ERROR when encounter SEU_Err" into integration 2022-11-28 15:08:25 +01:00
Sandrine Bailleux
086d981657 Merge changes I8667f362,Ia0bd832c into integration
* changes:
  feat(intel): setup FPGA interface for Agilex
  fix(intel): fix pinmux handoff bug on Agilex
2022-11-28 15:07:11 +01:00
Sandrine Bailleux
c00b06a41b Merge "fix(intel): fix sp_timer0 is not disabled in firewall on Agilex" into integration 2022-11-28 15:03:16 +01:00
Sandrine Bailleux
f6620acd05 Merge "fix(intel): remove checking on TEMP and VOLT checking for HWMON" into integration 2022-11-28 15:02:41 +01:00
Leo Yan
cffc956edf feat(qemu): support pointer authentication
This patch includes source code to support pointer authentication on
QEMU platform.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Change-Id: I582923080fe1d5baffd7d0ccfe83e3b28f910ae1
2022-11-28 14:19:05 +01:00
Sandrine Bailleux
27c07d0a00 Merge "fix(rss): remove null-terminator from RSS metadata" into integration 2022-11-28 12:46:56 +01:00
David Vincze
85a14bc0a9 fix(rss): remove null-terminator from RSS metadata
Remove the null-terminator of the string-like data items
from the RSS measurement's metadata. The 'version' and
'sw_type' items have an associated length value which
should not include a null-terminator when storing the
measurement.

Change-Id: Ia91ace2fff8b6f75686dd2e1862475268300bbdb
Signed-off-by: David Vincze <david.vincze@arm.com>
2022-11-25 18:31:14 +01:00
Joanna Farley
4ccbdd86bc Merge "fix(zynqmp): check return status of pm_get_api_version" into integration 2022-11-25 16:25:53 +01:00
Joanna Farley
896c0daf3e Merge "fix(versal): initialize the variable with value 0 in pm code" into integration 2022-11-25 16:24:53 +01:00
Mate Toth-Pal
3be9c27694 build: enable adding MbedTLS files for platform
The platform.mk can add extra MbedTLS source files to LIBMBEDTLS_SRC.

Change-Id: Ida9abfd59d8b02eae23ec0a7f326db060b42bf49
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
2022-11-25 10:06:10 +01:00
Mate Toth-Pal
6d0525aafe feat(lib/psa): add read_measurement API
This API is added for testing purposes. It makes possible to write test
cases that read measurements back after extending them, and compare
them to expected results.

Change-Id: Iec447d972fdd54a56ab933a065476e0f4d35a6fc
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
2022-11-25 10:00:13 +01:00
Naman Patel
c92ad369ca fix(zynqmp): check return status of pm_get_api_version
MISRA Violation: MISRA C-2012 Rule 17.7
- Check the return status of function pm_get_api_version
and return error in case of failure.

Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I69fb000c04f22996da7965a09a1797c7bfaad252
2022-11-24 05:30:23 -08:00
Naman Patel
cd73d62b0e fix(versal): initialize the variable with value 0 in pm code
Remove zeromem function as the array is already initialized
with value 0.

MISRA Violation: MISRA C-2012 Rule 9.1
- Initialize the array/variable with a value 0 to resolve
the misra warnings in pm_service component.

Signed-off-by: Naman Patel <naman.patel@amd.com>
Change-Id: I1a3d44a7ae4088a3034eb0119d82b99cd4617ccd
2022-11-24 05:25:48 -08:00
Manish Pandey
53f63eb0ff Merge "feat(qemu): increase size of bl2" into integration 2022-11-24 11:41:08 +01:00
Joanna Farley
0125e86b3b Merge "fix(docs): deprecate plat_convert_pk() in v2.9" into integration 2022-11-22 17:07:05 +01:00
Jit Loon Lim
4b3d323acd fix(intel): agilex bitstream pre-authenticate
HSD : To add in bitstream pre-authentication checking.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia8f1471a674ba16972927084f5fdc27c4ba93103
2022-11-22 23:57:43 +08:00
Jit Loon Lim
7f9e9e4b40 fix(intel): mailbox store QSPI ref clk in scratch reg
When HPS requests QSPI controller access the SDM returns the QSPI
reference clock frequency. Store the provided reference clock frequency
(in kHz) in BOOT_SCRATCH_COLD_0 register (bits [27:0]) as u-boot
QSPI driver expects this.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6b95c19db602387a79ff10abdebbc57abb0c07ff
2022-11-22 23:56:42 +08:00
Jit Loon Lim
68ac5fe14c fix(intel): remove checking on TEMP and VOLT checking for HWMON
Remove high level logic hardware channel checking on HWMON
TEMP and VOLT read.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I9102b7b4334cb95f0b622c498a6569328f534d42
2022-11-22 23:56:06 +08:00
Jit Loon Lim
8de7167eb6 fix(intel): fix sp_timer0 is not disabled in firewall on Agilex
sp_timer0 is not disabled in firewall on Agilex causing Zephyr is facing
issue to access the timer.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I0099e200d6c9ca435f46393c6ed9cbe387870af0
2022-11-22 23:55:02 +08:00
Jit Loon Lim
3905f57134 feat(intel): setup FPGA interface for Agilex
Enable/Disable FPGA interfaces based on handoff configuration.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5
2022-11-22 23:35:36 +08:00