Commit graph

8 commits

Author SHA1 Message Date
Tamas Ban
7f8589cdba refactor(tc): change all occurrences of RSS to RSE
Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Idec0bf7a90ae381f5bc968e1bb167daace24a11f
2024-04-22 15:44:38 +02:00
Boyan Karatotev
18f754a275 feat(tc): allow booting from DRAM
In some occasions it is useful to boot with the rest of system (RoS)
disabled. With no RoS there's no flash so we need to put images
somewhere and that's in the DRAM1 bank. If we want to access it it needs
to be mapped to memory.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I45e0fbb016e8f615d41b6ad9da0d1e7b466ece72
2024-02-26 13:40:21 +00:00
Tamas Ban
6f503e0eea feat(tc): add RSS SDS region right after SCMI payload
Add a second SDS region on the TC platform for communication with RSS.
RSS needs to share data with AP during early boot over shared memory
to support DPE. Reserve a memory region right after the SCMI secure
payload areas from unused memory.

Change-Id: I3a3a6ea5ce76531595c88754418602133a283c42
Signed-off-by: David Vincze <david.vincze@arm.com>
2024-02-13 14:36:14 +01:00
Madhukar Pappireddy
28b2d86cd2 feat(tc): allow secure watchdog timer to trigger periodically
This patch does the following:
  1. Configures SBSA secure watchdog timer as Group0 interrupt for
     TC platform while keeping it as Group1 secure interrupt for
     other CSS based SoCs.
  2. Programs the watchdog timer to trigger periodically
  3. Provides a Group0 interrupt handler for TC platform port to
     deactivate the EL3 interrupt due to expiry of secure watchdog
     timer and refresh it explicitly.

Change-Id: I3847d6eb7347c6ea0e527b97b096119ca1e6701b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2023-05-04 08:24:12 -05:00
Arvind Ram Prakash
42d4d3baac refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
	1. When BL2 is entry point into TF-A(no BL1)
	2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).

BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.

Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
2023-03-15 11:43:14 +00:00
Tamas Ban
6cb5d3268f feat(tc): enable RSS backend based measured boot
Measurements taken during boot are stored in RSS.
These measurements are included in the platform
attestation token.

Change-Id: Iac3356f813fb417315681c718839319832a76191
Signed-off-by: David Vincze <david.vincze@arm.com>
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
2022-10-07 11:32:48 +02:00
Usama Arif
34a87d74d9
feat(tc): populate HW_CONFIG in BL31
BL2 passes FW_CONFIG to BL31 which contains information
about different DTBs present. BL31 then uses FW_CONFIG
to get the base address of HW_CONFIG and populate fconf.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I0b4fc83e6e0a0b9401f692516654eb9a3b037616
2021-09-07 14:37:53 +01:00
Usama Arif
6ec0c65b09
feat(plat/arm): Introduce TC1 platform
This renames tc0 platform folder and files to tc, and introduces
TARGET_PLATFORM variable to account for the differences between
TC0 and TC1.

Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
2021-08-11 11:36:50 +01:00
Renamed from plat/arm/board/tc0/tc0_plat.c (Browse further)