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6 commits

Author SHA1 Message Date
Jit Loon Lim
150d2be0d2 fix(intel): fix hardcoded mpu frequency ticks 
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.

Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
 2023-12-18 10:12:29 +08:00
Sieu Mun Tang
02a9d70c4d feat(intel): implement timer init divider via CPU frequency for N5X 
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed
 2023-04-14 09:17:33 +08:00
Sieu Mun Tang
0d19eda0dd fix(intel): remove unused printout 
This patch is to remove unused printout.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I507210402dcbaf8369209308ae1fcedaccb0292d
 2022-05-13 16:46:25 +08:00
BenjaminLimJL
f65bdf3a54 feat(intel): implement timer init divider via cpu frequency. (#1) 
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422
 2022-05-06 17:37:45 +02:00
Tien Hock Loh
811af8b768 plat: intel: Additional instruction required to enable global timer 
There are additional instruction needed to enable the global timer.
This fixes the global timer initialization

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98
 2020-06-08 22:03:54 +00:00
Hadi Asyrafi
d8820789ca intel: Platform common code refactor 
Pull out common code from agilex and stratix10

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
 2019-08-01 16:39:27 +08:00
Renamed from plat/intel/soc/agilex/socfpga_delay_timer.c (Browse further)