The CLK_NAME_LEN variable is set to 15 but with more
hardening we get the following error for the
pss_alt_ref_clk name so bump the length slightly
to take all the requirements into account.
plat/xilinx/zynqmp/pm_service/pm_api_clock.c:2248:25: error: initializer-string for array of ‘char’ is too long [-Werror=unterminated-string-initialization]
2248 | .name = "pss_alt_ref_clk",
| ^~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Fixes: caae497df ("zynqmp: pm: Add clock control EEMI API and ioctl functions")
Change-Id: I399271dd257c6e40a2d319c47f2588a958a5491b
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
We have one entry per CPU features but most of the time we just add
CPU feature and its not touched again, so considering to generalize
anything with FEAT_XXXX additions to use `cpufeat` as subsection scope.
Also, some time we don't add a scope for CPU feature this causes problem
while generating release notes as CPU feature additions ends up in wrong
section.
Change-Id: Ibc80f6cdab9ae10ec3af1485640f46771b382da0
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
1. Turn on APU SMPU protection on MT8196.
2. Remove unused header file.
Change-Id: I58637b8dda4bf68253bc2329580963a8bd9cca8b
Signed-off-by: Karl Li <karl.li@mediatek.com>
Implement stub functions for the MMinfra (Multimedia Infrastructure)
driver to ensure that the build can pass when a prebuilt library is
not available.
Change-Id: Iadac654950c868d3743b13a1d6f7ab5d1015fb86
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
The commit 427e46ddea ("fix(xilinx): fix sending sgi to linux")
removed code which called write_icc_asgi1r_el1() but function itself
wasn't removed.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I95a1424b0546f3f4a5e4611de34441b96e70b7d3
When the SPD_spmd configuration is disabled, the compiler complaints:
plat/arm/board/tc/tc_bl2_dpe.c:234:22: error: unused variable 'array_size' [-Werror=unused-variable]
234 | const size_t array_size = ARRAY_SIZE(tc_dpe_metadata);
| ^~~~~~~~~~
plat/arm/board/tc/tc_bl2_dpe.c:233:16: error: unused variable 'i' [-Werror=unused-variable]
233 | size_t i;
| ^
cc1: all warnings being treated as errors
Move variable declarations into the code chunk protected by the SPD_spmd
configuration.
Change-Id: I1a3889938e2d4ec5efec516e9ef54034f9d711b2
Signed-off-by: Leo Yan <leo.yan@arm.com>
These specify the addresses of the MPAM registers in the MCN block. Note
that these are enabled for TC4 FPGA only as the MPAM devices are not
available on FVP.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: I105cd21952c2bd4fac5a06c84c0a93217b5e1312
This node specifies the location of the MPAM registers for the DSU.
Rename the node to clarify this.
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ie870a7f31acbc44dd943e76896219b9bbdd7d5b4
* changes:
feat(mt8196): add vcore dvfs drivers
feat(mt8196): add LPM v2 support
feat(mt8196): add SPM common version support
feat(mt8196): add SPM common driver support
feat(mt8196): add SPM basic features support
feat(mt8196): add SPM features support
feat(mt8196): enable PMIC low power setting
feat(mt8196): add mcdi driver
feat(mt8196): add pwr_ctrl module for CPU power management
feat(mt8196): add mcusys moudles for power management
feat(mt8196): add CPC module for power management
feat(mt8196): add topology module for power management
feat(mt8196): add SPMI driver
feat(mt8196): add PMIC driver
DCM means dynamic clock management, and it can dynamically slow down
or gate clocks during CPU or bus idle.
Add MCUSYS or bus related DCM drivers.
Enable MCUSYS or bus related DCM by default.
Signed-off-by: Guangjie Song <guangjie.song@mediatek.com>
Change-Id: I40fc21f5808962ca46870a2f3b9963dc8088f877
CPU PMU types are not same for all CPUs on TC platforms, so define the
PMU node per microarchitecture.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ibbe8dacda695ccb45965c7f4680d4b03cffdb815
Distros (e.g. Buildroot and Android) can have different secure partition
layout.
This commit iterates the DPE metadata table and finds index (i) for the
first entry of the secure partition, connecting with the defined secure
partition number NUM_SP, so the last secure partition index is:
i + NUM_SP - 1
Instead of setting the certificate in hard code, dynamically enables the
certificate for the last secure partition base on calculated index.
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: Idd11b4f463bf5ccc8d82cd06bd21deeebbda67d9
The previous code used 64-bit registers as the target and source for
load and store operations on 32-bit hardware registers. In certain
cases (e.g., when using USART1 as the debug console), this could result
in deadlocks where the A35 gets stuck in a permanent loop due to test
conditions that are never fulfilled.
To resolve this issue, 32-bit registers are now used for these
operations.
Change-Id: Id2c03a1df26738fe815079da042cc2dd989f4f8e
Signed-off-by: Boerge Struempfel <boerge.struempfel@gmail.com>
This is an experimental change which (hopefully) enables Dependabot on
the LTS branches, and ensures that PRs touching the package management
files in the repository assign the proper developer(s) as reviewers.
Change-Id: Iefa2f46325514026969fabd08e550544dcb4a598
Signed-off-by: Chris Kay <chris.kay@arm.com>
Corrected the comment for the size of NRD_CSS_DRAM1_CARVEOUT_SIZE
(0x0C000000) from 117MB to 192MB
Signed-off-by: Rakshit Goyal <rakshit.goyal@arm.com>
Change-Id: I289d37f50e70b936f717d4579d73882fac28ee95
Generate the rules for calling 'tlc' tool, and generating
a partition package as a TL:
- The data is aligned to 4k.
- Using TE types 0x103 for FF-A manifest, and 0x106 for
FF-A SP binary.
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I1941e3e8f43d8dad33cdd0dea0571cf4a0d5e8f3
Calculate the secure partition number and saves it into the defined
macro NUM_SP.
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Change-Id: I4175a10d315482b65fd0f3eed4c6fd1e1e2b5e4d
Updating LTS maintainers list as agreed with other LTS
maintainers.
Change-Id: Ibf087c6b0e24d6faa9dafb6f8a0955a47f583f28
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
MDCR_EL3 register will context switch across all worlds. Thus the pmuv3
init has to be part of context management initialization.
Change-Id: I10ef7a3071c0fc5c11a93d3c9c2a95ec8c6493bf
Signed-off-by: Mateusz Sulimowicz <matsul@google.com>
Extend board detection with saving information about PS,
PMC and RTL versions. Variables can be use to cover
different behavior based on version and version
information is also printed for chip identification.
Change-Id: Ia37418f6a31426a5763fb89fc76fef91d09df155
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,
External LLC is present on TC4 systems in MCN but it is not enabled in
CPU registers so enable it.
On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC
so take care of that as well.
Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
This patch adds the routing table addresses required for LCA
enablement on RD-N2-Cfg2. CMN on RD-N2-Cfg2 uses AXI Stream IDs
to route LCA connections to the correct downstream tx_cxs_a4s
port. The data programmed in the routing table are the A4S IDs
of each chip.
Change-Id: I46e558f3be7f0d51b768b7c5586f15e6bc517f3a
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
This patch adds the routing table addresses required for LCA
enablement on RD-V3-Cfg2. Since LCA connection on rdv3 uses ACE5L
instead of A4S, the addresses programmed in the routing table is
the address of memory mapped HNI with chip offset.
Change-Id: Ic235983d63e8ab3492ae566b68841d0659724e45
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
This patch adds support for Local Chip Addressing (LCA). In a multi-chip
system, enablig LCA allows each GIC Distributor to maintain its own
version of routing table. This feature is activated when the
GICD_CFGID.LCA bit is set to 1.
The existing `gic600_multichip_data` data structure did not account for
the LCA feature. To support LCA:
- `rt_owner_base` is replaced by `base_addrs[]`. This is required
because each GICD in the system needs to be configured independently,
and their base addresses must be passed to the driver.
- `chip_addrs` is changed from 1D to 2D array to store the routing table
for each chip's GICD. The entries in `chip_addrs` are configuration
dependent, as the GIC specification does not enforce this.
On a multi-chip platform with chip count N where LCA is enabled by
default, the `gic600_multichip_data` structure should contain all copies
of the routing table (N*N entries). On platforms where LCA is not
supported, only the first sub-array with N entries is required. The
function signature of `gic600_multichip_init` remains unchanged, but if
the LCA feature is enabled, the driver will expect the routing table
configuration in the described format.
Change-Id: I8830c2cf90db6a0cae78e99914cd32c637284a2b
Signed-off-by: Jerry Wang <Jerry.Wang4@arm.com>
