Commit graph

1988 commits

Author SHA1 Message Date
Boyan Karatotev
291be198fa docs: describe the new warning levels
When -Wextra was added, the warning levels changed their meaning. Add a
description in the build option section and leave the security hardening
section as mostly a pointer to it.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iabf2f598d0bf3e865c9b991c5d44d2acb9572bd5
2022-12-12 11:29:10 +00:00
Boyan Karatotev
228b06a535 docs(porting-guide): update a reference
The BL31 part has been there forever and the PSCI reference is neither
at section 3.3 or directly below. Update this to locate the section more
easily.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I9a86e4ef13d1ac5da743917493f63ddd7690e087
2022-12-01 16:17:34 +00:00
Lauren Wehrmeister
d3d2a5a484 Merge "fix(cpus): workaround for Cortex-X3 erratum 2615812" into integration 2022-11-28 18:15:06 +01:00
Yann Gautier
e0f58c7fb6 fix(docs): deprecate plat_convert_pk() in v2.9
The deprecation was tagged "Next release after 2.8". Now there is a 2.9
planned, directly use this version.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I0727eebc4a3800dafafc4166b0c2c40a12c90b4b
2022-11-22 15:15:46 +01:00
Manish Pandey
9881bb93a3 Merge "docs(spm): update threat model" into integration 2022-11-21 19:12:00 +01:00
Manish Pandey
9aef90cc7d Merge "docs(qemu): document steps to run in OpenCI" into integration 2022-11-21 18:55:23 +01:00
Madhukar Pappireddy
31b5b36c52 docs(spm): update threat model
Update SPM threat model for possible threats, from malicious
endpoints, related to interrupt management. The mitigations
are based on the guidance provided in FF-A v1.1 EAC0 spec.

Change-Id: Ib9e26e3f1c60fe3a2734a67de1dcf1cea4883d38
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2022-11-21 10:53:48 -06:00
Harrison Mutai
a5667be075 docs(qemu): document steps to run in OpenCI
Add details on how to run QEMU in OpenCI, and what tests are currently
supported.

Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
Change-Id: I291e4eb64a58c766519ff7dcac4841ae75c3934e
2022-11-21 16:45:24 +00:00
Manish Pandey
8613c15754 Merge "docs(changelog): changelog for v2.8 release" into integration 2022-11-18 18:28:52 +01:00
Joanna Farley
a846d33abc fix(docs): add v2.9 release schedule
Signed-off-by: Joanna Farley <Joanna.Farley@arm.com>
Change-Id: I082461d7d21f63e3b8cbee37e8f01b8128e4b5a0
2022-11-18 10:22:01 +02:00
Olivier Deprez
02fd5a1763 Merge changes I97687f18,I91d5718b into integration
* changes:
  docs(spm): interrupt handling guidance FF-A v1.1 EAC0
  docs(spm): partition runtime model and schedule modes
2022-11-17 11:14:05 +01:00
Harrison Mutai
c7e698cfde fix(cpus): workaround for Cortex-X3 erratum 2615812
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1, and is still open. The workaround is to disable
the use of the Full Retention power mode in the core (setting
WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000).

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2055130/latest

Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
2022-11-17 09:41:40 +00:00
Olivier Deprez
8fca0cdbee Merge changes from topic "ja/spm_doc" into integration
* changes:
  docs(spm): ff-a v1.1 indirect message
  docs(spm): s-el0 partition support update
2022-11-17 10:04:49 +01:00
Madhukar Pappireddy
06afdd1e7a docs(spm): interrupt handling guidance FF-A v1.1 EAC0
This patch documents the actions taken by Hafnium SPMC in response
to non-secure and secure interrupts.

Change-Id: I97687f188ca97aeb255e3e5b55d44ddf5d66b6e0
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2022-11-16 14:28:37 -06:00
laurenw-arm
0fa7fe59f3 docs(changelog): changelog for v2.8 release
Change-Id: I1d99ea46ad527993ee786c34a67f94d74470f960
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2022-11-16 14:10:49 -06:00
Madhukar Pappireddy
03997f187c docs(spm): partition runtime model and schedule modes
This patch documents the support for partition runtime models, call
chains and schedule modes in Hafnium SPMC.

Change-Id: I91d5718bb2c21d475499e402f6f27076930336cb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2022-11-16 13:34:32 -06:00
Madhukar Pappireddy
b688120c98 Merge "docs(marvell): fix typo 8K => A8K" into integration 2022-11-16 18:13:48 +01:00
J-Alves
53e3b385f0 docs(spm): ff-a v1.1 indirect message
Update secure partition manager documentation to include
FF-A v1.1 indirect messaging implementation.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Ifbca45347f775080ef98ac896d31650204318ba4
2022-11-16 15:29:45 +00:00
Manish V Badarkhe
71061819aa Merge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration
* changes:
  docs: add top level section numbering
  docs(build): clarify getting started section
  docs(build): clarify docs building instructions
  fix(docs): prevent a sphinx warning
  fix(docs): prevent a virtual environment from failing a build
2022-11-16 16:18:54 +01:00
Olivier Deprez
54c52bcb76 Merge "docs(spm): update FF-A manifest binding" into integration 2022-11-16 15:39:08 +01:00
Boyan Karatotev
c65bf2d134 docs: add top level section numbering
Top level sections are not numbered. Adding numbers makes referring to
sections easier. For example the Maintainers page changes from
"about/3.1" to simply "1.3.1".

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: If90a18ee8d6a6858d58f0687f31ea62b69399e04
2022-11-16 14:06:48 +00:00
Boyan Karatotev
b50838bae7 docs(build): clarify getting started section
The Getting started section is very difficult to follow. Building the
fip comes before building the files it needs, the BL33 requirement is
given in a somewhat hand wavy way, and the Arm Developer website
download provides a lot of targets and the guide is not clear which ones
are needed on download.

Swapping the initial build and supporting tools sections makes the flow
more natural and the supporting tools section then becomes clear.
Explicitly mentioning the GCC targets avoids confusion for people less
familiar with the project (eg. new starters).

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I02e88f8c279db6d8eda68f634e8473c02b733963
2022-11-16 14:06:48 +00:00
Boyan Karatotev
8526472a46 docs(build): clarify docs building instructions
Using virtual environments with pip is a generally recommended good
practice but the docs do not acknowledge it. As a result fresh installs
might fail builds due to missing $PATH entries. The Prerequisites
section is also a bit verbose which is difficult to read.

This patch adds the virtual environment mention and clarifies wording.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iea447fb59dc471a502454650c8548192d93ba879
2022-11-16 14:06:48 +00:00
Boyan Karatotev
e48b1f8c48 fix(docs): prevent a sphinx warning
Some newer versions of sphinx (tried on v5.3) will warn about language
being None which will fail the build. Change it to the default (en) to
prevent this.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ie0570481f42aeb293e885ca936e0765f6cb299a8
2022-11-16 14:06:48 +00:00
Boyan Karatotev
3fd1fe388e fix(docs): prevent a virtual environment from failing a build
sphinx-build is passed a blanket "." to build all docs. However, if a
virtual environment is placed within the docs directory, sphinx will try
to build it which will fail due to some weird files it has.

This excludes the most common virtual environment directories from the
build to prevent this.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ieeb14cfc5730d21c986611feb0ed379c58dfcae2
2022-11-16 14:06:48 +00:00
Boyan Karatotev
068d92122a fix(docs): unify referenced Ubuntu versions
Documentation is inconsistent when referring to Ubuntu versioning.
Change this to a single reference that is consistent with the stated
version for TF-A tests.

The change was tested with a full build on a clean install of Ubuntu 20.04.

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ibb135ed938e9d92332668fa5caf274cf61b822d3
2022-11-15 17:44:01 +00:00
J-Alves
c8e49504dd docs(spm): s-el0 partition support update
S-EL0 partitions already support indirect messaging and notifications
so add that to supported features.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: I08e04593653ba38a2b82395f6f2d3ca7b212d494
2022-11-15 11:03:50 +00:00
Manish Pandey
e1d24114a6 Merge changes I256959d7,I721376bf into integration
* changes:
  fix(cpus): remove plat_can_cmo check for aarch32
  fix(cpus): update doc and check for plat_can_cmo
2022-11-14 15:54:27 +01:00
Okash Khawaja
a2e0123484 fix(cpus): update doc and check for plat_can_cmo
plat_can_cmo must not clobber x1 but the doc doesn't mention that. This
patch updates the doc to mention x1. It also adds check for plat_can_cmo
to `dcsw_op_louis` which was missed out in original patch.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I721376bf3726520d0d5b0df0f33f98ce92257287
2022-11-14 15:31:12 +01:00
Yann Gautier
981b9dcb87 refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE
The code managing legacy boot (without FIP) that was under
STM32MP_USE_STM32IMAGE flag is remove.

Change-Id: I04452453ed84567b0de39e900594a81526562259
Signed-off-by: Yann Gautier <yann.gautier@st.com>
2022-11-14 14:14:48 +01:00
Lionel Debieve
b82a30c297 docs(st): update documentation for TRUSTED_BOARD_BOOT
Update the documentation to indicate commands needed for
TRUSTED_BOARD_BOOT management.

Change-Id: I7b8781eaa7f8b6b8d675a625c7ff2e1ee767222a
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2022-11-14 11:25:01 +01:00
Nicolas Toromanoff
40f9f644e8 feat(auth): allow to verify PublicKey with platform format PK
In some platform the digest of the public key saved in the OTP is not
the digest of the exact same public key buffer needed to check the
signature. Typically, platform checks signature using the DER ROTPK
whereas some others add some related information. Add a new platform
weak function to transform the public key buffer used by
verify_signature to a platform specific public key.

Mark this new weak function as deprecated as it will be replaced
by another framework implementation.

Change-Id: I71017b41e3eca9398cededf317ad97e9b511be5f
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2022-11-14 11:25:01 +01:00
Lionel Debieve
e78ba69e35 feat(cert-create): update for ECDSA brainpoolP256r/t1 support
Updated cert_tool to be able to select brainpool P256r/t1
or NIST prim256v1 curve for certificates signature.

Change-Id: I6e800144697069ea83660053b8ba6e21c229243a
Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@foss.st.com>
2022-11-14 11:25:01 +01:00
Manish V Badarkhe
797d7446a0 Merge "refactor(security): add OpenSSL 1.x compatibility" into integration 2022-11-11 19:59:58 +01:00
Juan Pablo Conde
cf2dd17ddd refactor(security): add OpenSSL 1.x compatibility
When updated to work with OpenSSL 3.0, the host tools lost their
compatibility with previous versions (1.x) of OpenSSL. This is
mainly due to the fact that 1.x APIs became deprecated in 3.0 and
therefore their use cause compiling errors. In addition, updating
for a newer version of OpenSSL meant improving the stability
against security threats. However, although version 1.1.1 is
now deprecated, it still receives security updates, so it would
not imply major security issues to keep compatibility with it too.

This patch adds backwards compatibility with OpenSSL 1.x versions
by adding back 1.x API code. It defines a macro USING_OPENSSL3,
which will select the appropriate OpenSSL API version depending on
the OpenSSL library path chosen (which is determined by the
already-existing OPENSSL_DIR variable).

In addition, cleanup items were packed in functions and moved to
the proper modules in order to make the code more maintainable and
legible.

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I8deceb5e419edc73277792861882404790ccd33c
2022-11-11 13:33:42 -05:00
Manish Pandey
7e88791a13 Merge "fix(docs): add LTS maintainers" into integration 2022-11-11 18:40:39 +01:00
Bipin Ravi
20a43156f7 Merge "feat(cpus): make cache ops conditional" into integration 2022-11-11 17:49:20 +01:00
Bipin Ravi
ab0d4d9d44 fix(docs): add LTS maintainers
Adding the  maintainers for the TF-A LTS releases.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I683885b8b52c0d004218fa52f71a245bd26b1229
2022-11-11 10:08:05 -06:00
Manish V Badarkhe
42c70c08a8 build: deprecate Arm TC0 FVP platform
Arm has decided to deprecate the TC0 platform. The development of
software and fast models for TC0 platform has been discontinued.
TC0 platform has been superseded by the TC1 and TC2 platforms,
which are already supported in TF-A and CI repositories.

Change-Id: I0269816a6ee733f732669027eae4e14cd60b6084
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2022-11-11 09:43:21 +00:00
Bipin Ravi
2b138c6b31 Merge "fix(cpus): workaround for Cortex-A77 erratum 2743100" into integration 2022-11-11 05:35:21 +01:00
Joanna Farley
79bf51c2ff Merge "fix(docs): update maintainers list" into integration 2022-11-11 01:02:44 +01:00
Manish Pandey
f23ce63905 fix(docs): update maintainers list
As part of release process revisit list of maintainers to keep
it updated.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I63b87265a6bff00ad05d8b3b7cad694cdf48e9ea
2022-11-10 19:40:29 +00:00
Manish V Badarkhe
a06c5cad54 Merge "chore(docs): fix broken url references to arm procedure call" into integration 2022-11-10 19:25:01 +01:00
Olivier Deprez
f41e23ea73 Merge changes from topic "mp/ras_refactoring" into integration
* changes:
  docs: document do_panic() and panic() helper functions
  fix(ras): restrict RAS support for NS world
2022-11-10 17:46:21 +01:00
Govindraj Raja
702b46cba3 chore(docs): fix broken url references to arm procedure call
Couple for urls under section: `5.6. Use of built-in C and libc
data types` from docs has broken urls since the new arm procedure
call doc is moved to be part of `ARM-software/abi-aa`.

Change-Id: Ied184ed56c8335d4cbc687e56962439091a18e42
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
2022-11-10 16:24:54 +00:00
Boyan Karatotev
4fdeaffe86 fix(cpus): workaround for Cortex-A77 erratum 2743100
Cortex-A77 erratum 2743100 is a Cat B erratum that applies to revisions
r0p0, r1p0, r1p1, and is still open. The workaround is to insert a dsb
before the isb in the power down sequence.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1152370/latest

Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I8e49a2dac8611f31ace249a17ae7a90cd60e742a
2022-11-10 15:51:16 +00:00
Okash Khawaja
04c7303b9c feat(cpus): make cache ops conditional
When a core is in debug recovery mode its caches are not invalidated
upon reset, so the L1 and L2 cache contents from before reset are
observable after reset. Similarly, debug recovery mode of DynamIQ
cluster ensures that contents of the shared L3 cache are also not
invalidated upon transition to On mode.

Booting cores in debug recovery mode means booting with caches disabled
and preserving the caches until a point where software can dump the
caches and retrieve their contents. TF-A however unconditionally cleans
and invalidates caches at multiple points during boot. This can lead to
memory corruption as well as loss of cache contents to be used for
debugging.

This patch fixes this by calling a platform hook before performing CMOs
in helper routines in cache_helpers.S. The platform hook plat_can_cmo is
an assembly routine which must not clobber x2 and x3, and avoid using
stack. The whole checking is conditional upon `CONDITIONAL_CMO` which
can be set at compile time.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I172e999e4acd0f872c24056e647cc947ee54b193
2022-11-10 12:14:05 +00:00
Manish Pandey
0d41e17400 Merge "chore(docs): move deprecated platforms information around" into integration 2022-11-10 12:59:17 +01:00
Madhukar Pappireddy
c87e1f6228 Merge changes from topic "errata" into integration
* changes:
  fix(cpus): workaround for Cortex-A76 erratum 2743102
  fix(cpus): workaround for Neoverse N1 erratum 2743102
2022-11-09 21:20:24 +01:00
Manish V Badarkhe
00bf236e32 Merge "refactor(trng): cleanup the existing TRNG support" into integration 2022-11-09 17:30:17 +01:00