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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
feat(plat/rcar3): modify type for Internal function argument
Modify the type of the variable that stores the value for MPIDR in the internal function from uint64_t to u_register_t. Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ib5bda93d5432e0412132bddf41ead8ee3fcf9e46
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d9912cf3d1
commit
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3 changed files with 28 additions and 28 deletions
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@ -156,7 +156,7 @@ IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
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IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
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#endif
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uint32_t rcar_pwrc_status(uint64_t mpidr)
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uint32_t rcar_pwrc_status(u_register_t mpidr)
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{
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uint32_t ret = 0;
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uint64_t cm, cpu;
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@ -188,7 +188,7 @@ done:
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return ret;
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}
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static void scu_power_up(uint64_t mpidr)
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static void scu_power_up(u_register_t mpidr)
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{
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uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
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uint32_t c, sysc_reg_bit;
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@ -243,7 +243,7 @@ static void scu_power_up(uint64_t mpidr)
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;
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}
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void rcar_pwrc_cpuon(uint64_t mpidr)
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void rcar_pwrc_cpuon(u_register_t mpidr)
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{
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uint32_t res_data, on_data;
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uintptr_t res_reg, on_reg;
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@ -268,7 +268,7 @@ void rcar_pwrc_cpuon(uint64_t mpidr)
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rcar_lock_release();
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}
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void rcar_pwrc_cpuoff(uint64_t mpidr)
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void rcar_pwrc_cpuoff(u_register_t mpidr)
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{
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uint32_t c;
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uintptr_t reg;
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@ -289,7 +289,7 @@ void rcar_pwrc_cpuoff(uint64_t mpidr)
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rcar_lock_release();
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}
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void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
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void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr)
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{
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uint32_t c, shift_irq, shift_fiq;
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uintptr_t reg;
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@ -309,7 +309,7 @@ void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr)
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rcar_lock_release();
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}
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void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
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void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr)
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{
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uint32_t c, shift_irq, shift_fiq;
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uintptr_t reg;
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@ -331,8 +331,8 @@ void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
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void rcar_pwrc_all_disable_interrupt_wakeup(void)
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{
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uint32_t cl, cpu, cpu_num;
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uint64_t mpidr;
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uint32_t cpu_num;
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u_register_t cl, cpu, mpidr;
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const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
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RCAR_CLUSTER_CA57,
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@ -342,8 +342,8 @@ void rcar_pwrc_all_disable_interrupt_wakeup(void)
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for (cl = 0; cl < PLATFORM_CLUSTER_COUNT; cl++) {
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cpu_num = rcar_pwrc_get_cpu_num(cluster[cl]);
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for (cpu = 0; cpu < cpu_num; cpu++) {
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mpidr = (uint64_t)((cl << MPIDR_AFFINITY_BITS) | cpu);
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if (mpidr == (uint64_t)rcar_boot_mpidr) {
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mpidr = ((cl << MPIDR_AFFINITY_BITS) | cpu);
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if (mpidr == rcar_boot_mpidr) {
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rcar_pwrc_enable_interrupt_wakeup(mpidr);
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} else {
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rcar_pwrc_disable_interrupt_wakeup(mpidr);
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@ -352,7 +352,7 @@ void rcar_pwrc_all_disable_interrupt_wakeup(void)
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}
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}
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void rcar_pwrc_clusteroff(uint64_t mpidr)
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void rcar_pwrc_clusteroff(u_register_t mpidr)
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{
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uint32_t c, product, cut, reg;
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uintptr_t dst;
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@ -824,7 +824,7 @@ uint32_t rcar_pwrc_get_cluster(void)
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return RCAR_CLUSTER_A53A57;
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}
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uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr)
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uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr)
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{
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uint32_t c = rcar_pwrc_get_cluster();
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@ -877,7 +877,7 @@ done:
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}
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#endif
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int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr)
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int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr)
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{
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uint64_t i;
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uint64_t j;
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@ -41,19 +41,19 @@
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extern u_register_t rcar_boot_mpidr;
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#ifndef __ASSEMBLER__
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void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
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void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr);
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void rcar_pwrc_disable_interrupt_wakeup(u_register_t mpidr);
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void rcar_pwrc_enable_interrupt_wakeup(u_register_t mpidr);
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void rcar_pwrc_all_disable_interrupt_wakeup(void);
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void rcar_pwrc_clusteroff(uint64_t mpidr);
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void rcar_pwrc_cpuoff(uint64_t mpidr);
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void rcar_pwrc_cpuon(uint64_t mpidr);
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int32_t rcar_pwrc_cpu_on_check(uint64_t mpidr);
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void rcar_pwrc_clusteroff(u_register_t mpidr);
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void rcar_pwrc_cpuoff(u_register_t mpidr);
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void rcar_pwrc_cpuon(u_register_t mpidr);
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int32_t rcar_pwrc_cpu_on_check(u_register_t mpidr);
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void rcar_pwrc_setup(void);
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uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr);
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uint32_t rcar_pwrc_status(uint64_t mpidr);
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uint32_t rcar_pwrc_get_cpu_wkr(u_register_t mpidr);
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uint32_t rcar_pwrc_status(u_register_t mpidr);
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uint32_t rcar_pwrc_get_cluster(void);
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uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr);
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uint32_t rcar_pwrc_get_mpidr_cluster(u_register_t mpidr);
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uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type);
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void rcar_pwrc_restore_timer_state(void);
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void plat_secondary_reset(void);
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@ -42,7 +42,7 @@ extern void plat_rcar_gic_init(void);
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static uintptr_t rcar_sec_entrypoint;
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static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
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static void rcar_program_mailbox(u_register_t mpidr, uintptr_t address)
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{
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mailbox_t *rcar_mboxes = (mailbox_t *) MBOX_BASE;
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uint64_t linear_id = plat_core_pos_by_mpidr(mpidr);
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@ -75,7 +75,7 @@ static int rcar_pwr_domain_on(u_register_t mpidr)
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static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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uint32_t cluster_type = rcar_pwrc_get_cluster();
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unsigned long mpidr = read_mpidr_el1();
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u_register_t mpidr = read_mpidr_el1();
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if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
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if (cluster_type == RCAR_CLUSTER_A53A57)
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@ -93,7 +93,7 @@ static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
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#if RCAR_LSI != RCAR_D3
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uint32_t cluster_type = rcar_pwrc_get_cluster();
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#endif
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unsigned long mpidr = read_mpidr_el1();
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u_register_t mpidr = read_mpidr_el1();
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rcar_pwrc_disable_interrupt_wakeup(mpidr);
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gicv2_cpuif_disable();
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@ -112,7 +112,7 @@ static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
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static void rcar_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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uint32_t cluster_type = rcar_pwrc_get_cluster();
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unsigned long mpidr = read_mpidr_el1();
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u_register_t mpidr = read_mpidr_el1();
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if (CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
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return;
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@ -178,7 +178,7 @@ static void __dead2 rcar_system_off(void)
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ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
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#endif
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#else
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uint64_t cpu = read_mpidr_el1() & 0x0000ffff;
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u_register_t cpu = read_mpidr_el1() & 0x0000ffffU;
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int32_t rtn_on;
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rtn_on = rcar_pwrc_cpu_on_check(cpu);
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@ -271,7 +271,7 @@ static int rcar_validate_power_state(unsigned int power_state,
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#if RCAR_SYSTEM_SUSPEND
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static void rcar_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned long mpidr = read_mpidr_el1() & 0x0000ffffU;
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u_register_t mpidr = read_mpidr_el1() & 0x0000ffffU;
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int i;
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if (mpidr != rcar_boot_mpidr)
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