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feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53

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Add new function so that the value of bit at WUPMSKCA57/53,
which points to CPU other than the BOOT CPU, is 1 at initialization.
Modify sequence so that value of each bit for CPU at WUPMSKCA57/53 is
basically 0 and target bit value is changed to 1 only when CPU_OFF.

Signed-off-by: Koichi Yamaguchi <koichi.yamaguchi.zb@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Id5dafc04e1dbaf265c8b67b903c335bb1af49914
This commit is contained in:
Takuya Sakata 2021-11-02 20:30:02 +09:00 • committed by Marek Vasut
parent 82bb6c2e88
commit d9912cf3d1
4 changed files with 29 additions and 2 deletions
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23
drivers/renesas/common/pwrc/pwrc.c
View file

@ -329,6 +329,29 @@ void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr)
rcar_lock_release();
}
void rcar_pwrc_all_disable_interrupt_wakeup(void)
{
uint32_t cl, cpu, cpu_num;
uint64_t mpidr;
const uint32_t cluster[PLATFORM_CLUSTER_COUNT] = {
RCAR_CLUSTER_CA57,
RCAR_CLUSTER_CA53
};
for (cl = 0; cl < PLATFORM_CLUSTER_COUNT; cl++) {
cpu_num = rcar_pwrc_get_cpu_num(cluster[cl]);
for (cpu = 0; cpu < cpu_num; cpu++) {
mpidr = (uint64_t)((cl << MPIDR_AFFINITY_BITS) | cpu);
if (mpidr == (uint64_t)rcar_boot_mpidr) {
rcar_pwrc_enable_interrupt_wakeup(mpidr);
} else {
rcar_pwrc_disable_interrupt_wakeup(mpidr);
}
}
}
}
void rcar_pwrc_clusteroff(uint64_t mpidr)
{
uint32_t c, product, cut, reg;

3
drivers/renesas/common/pwrc/pwrc.h
View file

@ -38,9 +38,12 @@
#define RCAR_CLUSTER_CA53 (1U)
#define RCAR_CLUSTER_CA57 (2U)
extern u_register_t rcar_boot_mpidr;
#ifndef __ASSEMBLER__
void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr);
void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr);
void rcar_pwrc_all_disable_interrupt_wakeup(void);
void rcar_pwrc_clusteroff(uint64_t mpidr);
void rcar_pwrc_cpuoff(uint64_t mpidr);
void rcar_pwrc_cpuon(uint64_t mpidr);

1
plat/renesas/common/bl31_plat_setup.c
View file

@ -129,4 +129,5 @@ void bl31_platform_setup(void)
* functions
*/
rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
rcar_pwrc_all_disable_interrupt_wakeup();
}

4
plat/renesas/common/plat_pm.c
View file

@ -39,7 +39,6 @@
extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void);
extern u_register_t rcar_boot_mpidr;
static uintptr_t rcar_sec_entrypoint;
@ -82,8 +81,8 @@ static void rcar_pwr_domain_on_finish(const psci_power_state_t *target_state)
if (cluster_type == RCAR_CLUSTER_A53A57)
plat_cci_enable();
rcar_pwrc_disable_interrupt_wakeup(mpidr);
rcar_program_mailbox(mpidr, 0);
rcar_pwrc_enable_interrupt_wakeup(mpidr);
gicv2_cpuif_enable();
gicv2_pcpu_distif_init();
@ -96,6 +95,7 @@ static void rcar_pwr_domain_off(const psci_power_state_t *target_state)
#endif
unsigned long mpidr = read_mpidr_el1();
rcar_pwrc_disable_interrupt_wakeup(mpidr);
gicv2_cpuif_disable();
rcar_pwrc_cpuoff(mpidr);