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https://github.com/ARM-software/arm-trusted-firmware.git
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gic: Remove deprecated driver and interfaces
Change-Id: I567a406edb090ae9d109382f6874846a79dd7473 Co-authored-by: Roberto Vargas <roberto.vargas@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz
parent
e23e057e77
commit
f9ed3cb624
19 changed files with 27 additions and 1677 deletions
1
Makefile
1
Makefile
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@ -605,7 +605,6 @@ $(eval $(call assert_numeric,SMCCC_MAJOR_VERSION))
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$(eval $(call add_define,ARM_ARCH_MAJOR))
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$(eval $(call add_define,ARM_ARCH_MINOR))
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$(eval $(call add_define,ARM_GIC_ARCH))
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$(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
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$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
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$(eval $(call add_define,CTX_INCLUDE_FPREGS))
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@ -1274,47 +1274,22 @@ interrupts on the platform. To this end, the platform is expected to provide the
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GIC driver (either GICv2 or GICv3, as selected by the platform) with the
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interrupt configuration during the driver initialisation.
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There are two ways to specify secure interrupt configuration:
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Secure interrupt configuration are specified in an array of secure interrupt
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properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
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``interrupt_props`` member points to an array of interrupt properties. Each
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element of the array specifies the interrupt number and its configuration, viz.
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priority, group, configuration. Each element of the array shall be populated by
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the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
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#. Array of secure interrupt properties: In this scheme, in both GICv2 and GICv3
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driver data structures, the ``interrupt_props`` member points to an array of
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interrupt properties. Each element of the array specifies the interrupt
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number and its configuration, viz. priority, group, configuration. Each
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element of the array shall be populated by the macro ``INTR_PROP_DESC()``.
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The macro takes the following arguments:
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- 10-bit interrupt number,
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- 10-bit interrupt number,
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- 8-bit interrupt priority,
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- 8-bit interrupt priority,
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- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
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``INTR_TYPE_NS``),
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- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
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``INTR_TYPE_NS``),
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- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
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``GIC_INTR_CFG_EDGE``).
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#. Array of secure interrupts: In this scheme, the GIC driver is provided an
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array of secure interrupt numbers. The GIC driver, at the time of
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initialisation, iterates through the array and assigns each interrupt
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the appropriate group.
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- For the GICv2 driver, in ``gicv2_driver_data`` structure, the
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``g0_interrupt_array`` member of the should point to the array of
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interrupts to be assigned to *Group 0*, and the ``g0_interrupt_num``
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member of the should be set to the number of interrupts in the array.
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- For the GICv3 driver, in ``gicv3_driver_data`` structure:
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- The ``g0_interrupt_array`` member of the should point to the array of
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interrupts to be assigned to *Group 0*, and the ``g0_interrupt_num``
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member of the should be set to the number of interrupts in the array.
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- The ``g1s_interrupt_array`` member of the should point to the array of
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interrupts to be assigned to *Group 1 Secure*, and the
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``g1s_interrupt_num`` member of the should be set to the number of
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interrupts in the array.
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**Note that this scheme is deprecated.**
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- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
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``GIC_INTR_CFG_EDGE``).
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CPU specific operations framework
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---------------------------------
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@ -234,11 +234,6 @@ Common build options
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compiling TF-A. Its value must be a numeric, and defaults to 0. See also,
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*Armv8 Architecture Extensions* in `Firmware Design`_.
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- ``ARM_GIC_ARCH``: Choice of Arm GIC architecture version used by the Arm
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Legacy GIC driver for implementing the platform GIC API. This API is used
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by the interrupt management framework. Default is 2 (that is, version 2.0).
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This build option is deprecated.
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- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to
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cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
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is set, the functions which deal with MPIDR assume that the ``MT`` bit in
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@ -838,9 +833,6 @@ Arm FVP platform specific build options
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- ``FVP_GIC600`` : The GIC600 implementation of GICv3 is selected
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- ``FVP_GICV2`` : The GICv2 only driver is selected
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- ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
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- ``FVP_GICV3_LEGACY``: The Legacy GICv3 driver is selected (deprecated)
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Note: If TF-A is compiled with this option on FVPs with GICv3 hardware,
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then it configures the hardware to run in GICv2 emulation mode
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- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
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for functions that wait for an arbitrary time length (udelay and mdelay).
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@ -1,435 +0,0 @@
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/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <gic_v2.h>
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#include <gic_v3.h>
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#include <interrupt_mgmt.h>
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#include <platform.h>
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#include <stdint.h>
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/* Value used to initialize Non-Secure IRQ priorities four at a time */
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#define GICD_IPRIORITYR_DEF_VAL \
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(GIC_HIGHEST_NS_PRIORITY | \
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(GIC_HIGHEST_NS_PRIORITY << 8) | \
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(GIC_HIGHEST_NS_PRIORITY << 16) | \
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(GIC_HIGHEST_NS_PRIORITY << 24))
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static uintptr_t g_gicc_base;
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static uintptr_t g_gicd_base;
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static uintptr_t g_gicr_base;
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static const unsigned int *g_irq_sec_ptr;
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static unsigned int g_num_irqs;
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/*******************************************************************************
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* This function does some minimal GICv3 configuration. The Firmware itself does
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* not fully support GICv3 at this time and relies on GICv2 emulation as
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* provided by GICv3. This function allows software (like Linux) in later stages
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* to use full GICv3 features.
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******************************************************************************/
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static void gicv3_cpuif_setup(void)
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{
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unsigned int val;
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uintptr_t base;
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/*
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* When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
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* bit set. In order to allow interrupts to get routed to the CPU we
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* need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
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* to clear (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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assert(g_gicr_base);
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base = gicv3_get_rdist(g_gicr_base, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val &= ~WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to clear. */
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val = gicr_read_waker(base);
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while (val & WAKER_CA)
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val = gicr_read_waker(base);
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val = read_icc_sre_el3();
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write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
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isb();
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}
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/*******************************************************************************
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* This function does some minimal GICv3 configuration when cores go
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* down.
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******************************************************************************/
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static void gicv3_cpuif_deactivate(void)
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{
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unsigned int val;
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uintptr_t base;
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/*
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* When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
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* wait for GICR_WAKER.ChildrenAsleep to get set.
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* (GICv3 Architecture specification 5.4.23).
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* GICR_WAKER is NOT banked per CPU, compute the correct base address
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* per CPU.
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*/
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assert(g_gicr_base);
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base = gicv3_get_rdist(g_gicr_base, read_mpidr());
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if (base == (uintptr_t)NULL) {
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/* No re-distributor base address. This interface cannot be
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* configured.
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*/
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panic();
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}
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val = gicr_read_waker(base);
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val |= WAKER_PS;
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gicr_write_waker(base, val);
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dsb();
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/* We need to wait for ChildrenAsleep to set. */
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val = gicr_read_waker(base);
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while ((val & WAKER_CA) == 0)
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val = gicr_read_waker(base);
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}
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/*******************************************************************************
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* Enable secure interrupts and use FIQs to route them. Disable legacy bypass
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* and set the priority mask register to allow all interrupts to trickle in.
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******************************************************************************/
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void arm_gic_cpuif_setup(void)
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{
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unsigned int val;
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assert(g_gicc_base);
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val = gicc_read_iidr(g_gicc_base);
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/*
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* If GICv3 we need to do a bit of additional setup. We want to
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* allow default GICv2 behaviour but allow the next stage to
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* enable full gicv3 features.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
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gicv3_cpuif_setup();
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val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
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gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
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gicc_write_ctlr(g_gicc_base, val);
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}
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/*******************************************************************************
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* Place the cpu interface in a state where it can never make a cpu exit wfi as
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* as result of an asserted interrupt. This is critical for powering down a cpu
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******************************************************************************/
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void arm_gic_cpuif_deactivate(void)
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{
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unsigned int val;
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/* Disable secure, non-secure interrupts and disable their bypass */
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assert(g_gicc_base);
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val = gicc_read_ctlr(g_gicc_base);
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val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
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val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
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gicc_write_ctlr(g_gicc_base, val);
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val = gicc_read_iidr(g_gicc_base);
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/*
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* If GICv3 we need to do a bit of additional setup. Make sure the
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* RDIST is put to sleep.
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*/
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
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gicv3_cpuif_deactivate();
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}
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/*******************************************************************************
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* Per cpu gic distributor setup which will be done by all cpus after a cold
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* boot/hotplug. This marks out the secure interrupts & enables them.
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******************************************************************************/
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void arm_gic_pcpu_distif_setup(void)
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{
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unsigned int index, irq_num, sec_ppi_sgi_mask;
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assert(g_gicd_base);
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/* Setup PPI priorities doing four at a time */
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for (index = 0; index < 32; index += 4) {
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gicd_write_ipriorityr(g_gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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assert(g_irq_sec_ptr);
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sec_ppi_sgi_mask = 0;
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/* Ensure all SGIs and PPIs are Group0 to begin with */
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gicd_write_igroupr(g_gicd_base, 0, 0);
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for (index = 0; index < g_num_irqs; index++) {
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irq_num = g_irq_sec_ptr[index];
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if (irq_num < MIN_SPI_ID) {
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/* We have an SGI or a PPI */
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sec_ppi_sgi_mask |= 1U << irq_num;
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gicd_set_ipriorityr(g_gicd_base, irq_num,
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GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_isenabler(g_gicd_base, irq_num);
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}
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}
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/*
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* Invert the bitmask to create a mask for non-secure PPIs and
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* SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
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* update the GICR_IGROUPR0 as well in case we are running on a GICv3
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* system. This is critical if GICD_CTLR.ARE_NS=1.
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*/
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gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask);
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}
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/*******************************************************************************
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* Get the current CPU bit mask from GICD_ITARGETSR0
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******************************************************************************/
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static unsigned int arm_gic_get_cpuif_id(void)
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{
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unsigned int val;
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val = gicd_read_itargetsr(g_gicd_base, 0);
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return val & GIC_TARGET_CPU_MASK;
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}
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/*******************************************************************************
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* Global gic distributor setup which will be done by the primary cpu after a
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* cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
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* then enables the secure GIC distributor interface.
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******************************************************************************/
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static void arm_gic_distif_setup(void)
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{
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unsigned int num_ints, ctlr, index, irq_num;
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uint8_t target_cpu;
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/* Disable the distributor before going further */
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assert(g_gicd_base);
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ctlr = gicd_read_ctlr(g_gicd_base);
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ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
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gicd_write_ctlr(g_gicd_base, ctlr);
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/*
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* Mark out non-secure SPI interrupts. The number of interrupts is
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* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
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*/
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num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
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num_ints = (num_ints + 1) << 5;
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for (index = MIN_SPI_ID; index < num_ints; index += 32)
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gicd_write_igroupr(g_gicd_base, index, ~0);
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/* Setup SPI priorities doing four at a time */
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for (index = MIN_SPI_ID; index < num_ints; index += 4) {
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gicd_write_ipriorityr(g_gicd_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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/* Read the target CPU mask */
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target_cpu = arm_gic_get_cpuif_id();
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/* Configure SPI secure interrupts now */
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assert(g_irq_sec_ptr);
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for (index = 0; index < g_num_irqs; index++) {
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irq_num = g_irq_sec_ptr[index];
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if (irq_num >= MIN_SPI_ID) {
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/* We have an SPI */
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gicd_clr_igroupr(g_gicd_base, irq_num);
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gicd_set_ipriorityr(g_gicd_base, irq_num,
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GIC_HIGHEST_SEC_PRIORITY);
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gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
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gicd_set_isenabler(g_gicd_base, irq_num);
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}
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}
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/*
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* Configure the SGI and PPI. This is done in a separated function
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* because each CPU is responsible for initializing its own private
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* interrupts.
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*/
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arm_gic_pcpu_distif_setup();
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gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
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}
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/*******************************************************************************
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* Initialize the ARM GIC driver with the provided platform inputs
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******************************************************************************/
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void arm_gic_init(uintptr_t gicc_base,
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uintptr_t gicd_base,
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uintptr_t gicr_base,
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const unsigned int *irq_sec_ptr,
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unsigned int num_irqs)
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{
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unsigned int val;
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assert(gicc_base);
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assert(gicd_base);
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assert(irq_sec_ptr);
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g_gicc_base = gicc_base;
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g_gicd_base = gicd_base;
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val = gicc_read_iidr(g_gicc_base);
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if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
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assert(gicr_base);
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g_gicr_base = gicr_base;
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}
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g_irq_sec_ptr = irq_sec_ptr;
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g_num_irqs = num_irqs;
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}
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/*******************************************************************************
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* Setup the ARM GIC CPU and distributor interfaces.
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******************************************************************************/
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void arm_gic_setup(void)
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{
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arm_gic_cpuif_setup();
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arm_gic_distif_setup();
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}
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/*******************************************************************************
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* An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
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* The interrupt controller knows which pin/line it uses to signal a type of
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* interrupt. This function provides a common implementation of
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* plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
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* across platforms. It lets the interrupt management framework determine
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* for a type of interrupt and security state, which line should be used in the
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* SCR_EL3 to control its routing to EL3. The interrupt line is represented as
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* the bit position of the IRQ or FIQ bit in the SCR_EL3.
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******************************************************************************/
|
||||
uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
|
||||
uint32_t security_state)
|
||||
{
|
||||
assert(type == INTR_TYPE_S_EL1 ||
|
||||
type == INTR_TYPE_EL3 ||
|
||||
type == INTR_TYPE_NS);
|
||||
|
||||
assert(sec_state_is_valid(security_state));
|
||||
|
||||
/*
|
||||
* We ignore the security state parameter under the assumption that
|
||||
* both normal and secure worlds are using ARM GICv2. This parameter
|
||||
* will be used when the secure world starts using GICv3.
|
||||
*/
|
||||
#if ARM_GIC_ARCH == 2
|
||||
return gicv2_interrupt_type_to_line(g_gicc_base, type);
|
||||
#else
|
||||
#error "Invalid ARM GIC architecture version specified for platform port"
|
||||
#endif /* ARM_GIC_ARCH */
|
||||
}
|
||||
|
||||
#if ARM_GIC_ARCH == 2
|
||||
/*******************************************************************************
|
||||
* This function returns the type of the highest priority pending interrupt at
|
||||
* the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
|
||||
* interrupt pending.
|
||||
******************************************************************************/
|
||||
uint32_t arm_gic_get_pending_interrupt_type(void)
|
||||
{
|
||||
uint32_t id;
|
||||
|
||||
assert(g_gicc_base);
|
||||
id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
|
||||
|
||||
/* Assume that all secure interrupts are S-EL1 interrupts */
|
||||
if (id < 1022)
|
||||
return INTR_TYPE_S_EL1;
|
||||
|
||||
if (id == GIC_SPURIOUS_INTERRUPT)
|
||||
return INTR_TYPE_INVAL;
|
||||
|
||||
return INTR_TYPE_NS;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the id of the highest priority pending interrupt at
|
||||
* the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
|
||||
* interrupt pending.
|
||||
******************************************************************************/
|
||||
uint32_t arm_gic_get_pending_interrupt_id(void)
|
||||
{
|
||||
uint32_t id;
|
||||
|
||||
assert(g_gicc_base);
|
||||
id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
|
||||
|
||||
if (id < 1022)
|
||||
return id;
|
||||
|
||||
if (id == 1023)
|
||||
return INTR_ID_UNAVAILABLE;
|
||||
|
||||
/*
|
||||
* Find out which non-secure interrupt it is under the assumption that
|
||||
* the GICC_CTLR.AckCtl bit is 0.
|
||||
*/
|
||||
return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This functions reads the GIC cpu interface Interrupt Acknowledge register
|
||||
* to start handling the pending interrupt. It returns the contents of the IAR.
|
||||
******************************************************************************/
|
||||
uint32_t arm_gic_acknowledge_interrupt(void)
|
||||
{
|
||||
assert(g_gicc_base);
|
||||
return gicc_read_IAR(g_gicc_base);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This functions writes the GIC cpu interface End Of Interrupt register with
|
||||
* the passed value to finish handling the active interrupt
|
||||
******************************************************************************/
|
||||
void arm_gic_end_of_interrupt(uint32_t id)
|
||||
{
|
||||
assert(g_gicc_base);
|
||||
gicc_write_EOIR(g_gicc_base, id);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the type of the interrupt id depending upon the group
|
||||
* this interrupt has been configured under by the interrupt controller i.e.
|
||||
* group0 or group1.
|
||||
******************************************************************************/
|
||||
uint32_t arm_gic_get_interrupt_type(uint32_t id)
|
||||
{
|
||||
uint32_t group;
|
||||
|
||||
assert(g_gicd_base);
|
||||
group = gicd_get_igroupr(g_gicd_base, id);
|
||||
|
||||
/* Assume that all secure interrupts are S-EL1 interrupts */
|
||||
if (group == GRP0)
|
||||
return INTR_TYPE_S_EL1;
|
||||
else
|
||||
return INTR_TYPE_NS;
|
||||
}
|
||||
|
||||
#else
|
||||
#error "Invalid ARM GIC architecture version specified for platform port"
|
||||
#endif /* ARM_GIC_ARCH */
|
||||
|
|
@ -1,284 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <assert.h>
|
||||
#include <gic_v2.h>
|
||||
#include <interrupt_mgmt.h>
|
||||
#include <mmio.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC Distributor interface accessors for reading entire registers
|
||||
******************************************************************************/
|
||||
|
||||
unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> IGROUPR_SHIFT;
|
||||
return mmio_read_32(base + GICD_IGROUPR + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ISENABLER_SHIFT;
|
||||
return mmio_read_32(base + GICD_ISENABLER + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ICENABLER_SHIFT;
|
||||
return mmio_read_32(base + GICD_ICENABLER + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ISPENDR_SHIFT;
|
||||
return mmio_read_32(base + GICD_ISPENDR + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ICPENDR_SHIFT;
|
||||
return mmio_read_32(base + GICD_ICPENDR + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ISACTIVER_SHIFT;
|
||||
return mmio_read_32(base + GICD_ISACTIVER + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ICACTIVER_SHIFT;
|
||||
return mmio_read_32(base + GICD_ICACTIVER + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> IPRIORITYR_SHIFT;
|
||||
return mmio_read_32(base + GICD_IPRIORITYR + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ITARGETSR_SHIFT;
|
||||
return mmio_read_32(base + GICD_ITARGETSR + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> ICFGR_SHIFT;
|
||||
return mmio_read_32(base + GICD_ICFGR + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> CPENDSGIR_SHIFT;
|
||||
return mmio_read_32(base + GICD_CPENDSGIR + (n << 2));
|
||||
}
|
||||
|
||||
unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned n = id >> SPENDSGIR_SHIFT;
|
||||
return mmio_read_32(base + GICD_SPENDSGIR + (n << 2));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC Distributor interface accessors for writing entire registers
|
||||
******************************************************************************/
|
||||
|
||||
void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> IGROUPR_SHIFT;
|
||||
mmio_write_32(base + GICD_IGROUPR + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ISENABLER_SHIFT;
|
||||
mmio_write_32(base + GICD_ISENABLER + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ICENABLER_SHIFT;
|
||||
mmio_write_32(base + GICD_ICENABLER + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ISPENDR_SHIFT;
|
||||
mmio_write_32(base + GICD_ISPENDR + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ICPENDR_SHIFT;
|
||||
mmio_write_32(base + GICD_ICPENDR + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ISACTIVER_SHIFT;
|
||||
mmio_write_32(base + GICD_ISACTIVER + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ICACTIVER_SHIFT;
|
||||
mmio_write_32(base + GICD_ICACTIVER + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> IPRIORITYR_SHIFT;
|
||||
mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ITARGETSR_SHIFT;
|
||||
mmio_write_32(base + GICD_ITARGETSR + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> ICFGR_SHIFT;
|
||||
mmio_write_32(base + GICD_ICFGR + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> CPENDSGIR_SHIFT;
|
||||
mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val);
|
||||
}
|
||||
|
||||
void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val)
|
||||
{
|
||||
unsigned n = id >> SPENDSGIR_SHIFT;
|
||||
mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC Distributor interface accessors for individual interrupt manipulation
|
||||
******************************************************************************/
|
||||
unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
|
||||
unsigned int reg_val = gicd_read_igroupr(base, id);
|
||||
|
||||
return (reg_val >> bit_num) & 0x1;
|
||||
}
|
||||
|
||||
void gicd_set_igroupr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
|
||||
unsigned int reg_val = gicd_read_igroupr(base, id);
|
||||
|
||||
gicd_write_igroupr(base, id, reg_val | (1 << bit_num));
|
||||
}
|
||||
|
||||
void gicd_clr_igroupr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
|
||||
unsigned int reg_val = gicd_read_igroupr(base, id);
|
||||
|
||||
gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num));
|
||||
}
|
||||
|
||||
void gicd_set_isenabler(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
|
||||
|
||||
gicd_write_isenabler(base, id, (1 << bit_num));
|
||||
}
|
||||
|
||||
void gicd_set_icenabler(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
|
||||
|
||||
gicd_write_icenabler(base, id, (1 << bit_num));
|
||||
}
|
||||
|
||||
void gicd_set_ispendr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
|
||||
|
||||
gicd_write_ispendr(base, id, (1 << bit_num));
|
||||
}
|
||||
|
||||
void gicd_set_icpendr(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
|
||||
|
||||
gicd_write_icpendr(base, id, (1 << bit_num));
|
||||
}
|
||||
|
||||
void gicd_set_isactiver(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
|
||||
|
||||
gicd_write_isactiver(base, id, (1 << bit_num));
|
||||
}
|
||||
|
||||
void gicd_set_icactiver(uintptr_t base, unsigned int id)
|
||||
{
|
||||
unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1);
|
||||
|
||||
gicd_write_icactiver(base, id, (1 << bit_num));
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure that the interrupt's group is set before expecting
|
||||
* this function to do its job correctly.
|
||||
*/
|
||||
void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
|
||||
{
|
||||
/*
|
||||
* Enforce ARM recommendation to manage priority values such
|
||||
* that group1 interrupts always have a lower priority than
|
||||
* group0 interrupts.
|
||||
* Note, lower numerical values are higher priorities so the comparison
|
||||
* checks below are reversed from what might be expected.
|
||||
*/
|
||||
assert(gicd_get_igroupr(base, id) == GRP1 ?
|
||||
pri >= GIC_HIGHEST_NS_PRIORITY &&
|
||||
pri <= GIC_LOWEST_NS_PRIORITY :
|
||||
pri >= GIC_HIGHEST_SEC_PRIORITY &&
|
||||
pri <= GIC_LOWEST_SEC_PRIORITY);
|
||||
|
||||
mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK);
|
||||
}
|
||||
|
||||
void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target)
|
||||
{
|
||||
mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function allows the interrupt management framework to determine (through
|
||||
* the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to
|
||||
* route it to EL3. The interrupt line is represented as the bit position of the
|
||||
* IRQ or FIQ bit in the SCR_EL3.
|
||||
******************************************************************************/
|
||||
uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type)
|
||||
{
|
||||
uint32_t gicc_ctlr;
|
||||
|
||||
/* Non-secure interrupts are signalled on the IRQ line always */
|
||||
if (type == INTR_TYPE_NS)
|
||||
return __builtin_ctz(SCR_IRQ_BIT);
|
||||
|
||||
/*
|
||||
* Secure interrupts are signalled using the IRQ line if the FIQ_EN
|
||||
* bit is not set else they are signalled using the FIQ line.
|
||||
*/
|
||||
gicc_ctlr = gicc_read_ctlr(cpuif_base);
|
||||
if (gicc_ctlr & FIQ_EN)
|
||||
return __builtin_ctz(SCR_FIQ_BIT);
|
||||
else
|
||||
return __builtin_ctz(SCR_IRQ_BIT);
|
||||
}
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <debug.h>
|
||||
#include <gic_v3.h>
|
||||
|
||||
uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr)
|
||||
{
|
||||
uint32_t cpu_aff, gicr_aff;
|
||||
uint64_t gicr_typer;
|
||||
uintptr_t addr;
|
||||
|
||||
/* Construct the affinity as used by GICv3. MPIDR and GIC affinity level
|
||||
* mask is the same.
|
||||
*/
|
||||
cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) <<
|
||||
GICV3_AFF0_SHIFT;
|
||||
cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) <<
|
||||
GICV3_AFF1_SHIFT;
|
||||
cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) <<
|
||||
GICV3_AFF2_SHIFT;
|
||||
cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) <<
|
||||
GICV3_AFF3_SHIFT;
|
||||
|
||||
addr = gicr_base;
|
||||
do {
|
||||
gicr_typer = gicr_read_typer(addr);
|
||||
|
||||
gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) &
|
||||
GICR_TYPER_AFF_MASK;
|
||||
if (cpu_aff == gicr_aff) {
|
||||
/* Disable this print for now as it appears every time
|
||||
* when using PSCI CPU_SUSPEND.
|
||||
* TODO: Print this only the first time for each CPU.
|
||||
* INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at %p\n",
|
||||
* mpidr, (void *) addr);
|
||||
*/
|
||||
return addr;
|
||||
}
|
||||
|
||||
/* TODO:
|
||||
* For GICv4 we need to adjust the Base address based on
|
||||
* GICR_TYPER.VLPIS
|
||||
*/
|
||||
addr += (1 << GICR_PCPUBASE_SHIFT);
|
||||
|
||||
} while (!(gicr_typer & GICR_TYPER_LAST));
|
||||
|
||||
/* If we get here we did not find a match. */
|
||||
ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr);
|
||||
return (uintptr_t)NULL;
|
||||
}
|
||||
|
|
@ -114,43 +114,6 @@ void gicv2_spis_configure_defaults(uintptr_t gicd_base)
|
|||
gicd_write_icfgr(gicd_base, index, 0U);
|
||||
}
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
/*******************************************************************************
|
||||
* Helper function to configure secure G0 SPIs.
|
||||
******************************************************************************/
|
||||
void gicv2_secure_spis_configure(uintptr_t gicd_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list)
|
||||
{
|
||||
unsigned int index, irq_num;
|
||||
|
||||
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
|
||||
if (num_ints != 0U)
|
||||
assert(sec_intr_list != NULL);
|
||||
|
||||
for (index = 0; index < num_ints; index++) {
|
||||
irq_num = sec_intr_list[index];
|
||||
if (irq_num >= MIN_SPI_ID) {
|
||||
/* Configure this interrupt as a secure interrupt */
|
||||
gicd_clr_igroupr(gicd_base, irq_num);
|
||||
|
||||
/* Set the priority of this interrupt */
|
||||
gicd_set_ipriorityr(gicd_base,
|
||||
irq_num,
|
||||
GIC_HIGHEST_SEC_PRIORITY);
|
||||
|
||||
/* Target the secure interrupts to primary CPU */
|
||||
gicd_set_itargetsr(gicd_base, irq_num,
|
||||
gicv2_get_cpuif_id(gicd_base));
|
||||
|
||||
/* Enable this interrupt */
|
||||
gicd_set_isenabler(gicd_base, irq_num);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Helper function to configure properties of secure G0 SPIs.
|
||||
******************************************************************************/
|
||||
|
|
@ -192,56 +155,6 @@ void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
|
|||
}
|
||||
}
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
/*******************************************************************************
|
||||
* Helper function to configure secure G0 SGIs and PPIs.
|
||||
******************************************************************************/
|
||||
void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list)
|
||||
{
|
||||
unsigned int index, irq_num, sec_ppi_sgi_mask = 0;
|
||||
|
||||
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
|
||||
assert(num_ints ? (uintptr_t)sec_intr_list : 1);
|
||||
|
||||
/*
|
||||
* Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
|
||||
* more scalable approach as it avoids clearing the enable bits in the
|
||||
* GICD_CTLR.
|
||||
*/
|
||||
gicd_write_icenabler(gicd_base, 0, ~0);
|
||||
|
||||
/* Setup the default PPI/SGI priorities doing four at a time */
|
||||
for (index = 0; index < MIN_SPI_ID; index += 4)
|
||||
gicd_write_ipriorityr(gicd_base,
|
||||
index,
|
||||
GICD_IPRIORITYR_DEF_VAL);
|
||||
|
||||
for (index = 0; index < num_ints; index++) {
|
||||
irq_num = sec_intr_list[index];
|
||||
if (irq_num < MIN_SPI_ID) {
|
||||
/* We have an SGI or a PPI. They are Group0 at reset */
|
||||
sec_ppi_sgi_mask |= 1U << irq_num;
|
||||
|
||||
/* Set the priority of this interrupt */
|
||||
gicd_set_ipriorityr(gicd_base,
|
||||
irq_num,
|
||||
GIC_HIGHEST_SEC_PRIORITY);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Invert the bitmask to create a mask for non-secure PPIs and
|
||||
* SGIs. Program the GICD_IGROUPR0 with this bit mask.
|
||||
*/
|
||||
gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask);
|
||||
|
||||
/* Enable the Group 0 SGIs and PPIs */
|
||||
gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Helper function to configure properties of secure G0 SGIs and PPIs.
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -79,27 +79,9 @@ void gicv2_pcpu_distif_init(void)
|
|||
assert(driver_data != NULL);
|
||||
assert(driver_data->gicd_base != 0U);
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (driver_data->interrupt_props != NULL) {
|
||||
#endif
|
||||
gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
|
||||
driver_data->interrupt_props,
|
||||
driver_data->interrupt_props_num);
|
||||
#if !ERROR_DEPRECATED
|
||||
} else {
|
||||
/*
|
||||
* Suppress deprecated declaration warnings in compatibility
|
||||
* function
|
||||
*/
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
|
||||
assert(driver_data->g0_interrupt_array);
|
||||
gicv2_secure_ppi_sgi_setup(driver_data->gicd_base,
|
||||
driver_data->g0_interrupt_num,
|
||||
driver_data->g0_interrupt_array);
|
||||
#pragma GCC diagnostic pop
|
||||
}
|
||||
#endif
|
||||
gicv2_secure_ppi_sgi_setup_props(driver_data->gicd_base,
|
||||
driver_data->interrupt_props,
|
||||
driver_data->interrupt_props_num);
|
||||
|
||||
/* Enable G0 interrupts if not already */
|
||||
ctlr = gicd_read_ctlr(driver_data->gicd_base);
|
||||
|
|
@ -129,30 +111,10 @@ void gicv2_distif_init(void)
|
|||
/* Set the default attribute of all SPIs */
|
||||
gicv2_spis_configure_defaults(driver_data->gicd_base);
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (driver_data->interrupt_props != NULL) {
|
||||
#endif
|
||||
gicv2_secure_spis_configure_props(driver_data->gicd_base,
|
||||
driver_data->interrupt_props,
|
||||
driver_data->interrupt_props_num);
|
||||
#if !ERROR_DEPRECATED
|
||||
} else {
|
||||
/*
|
||||
* Suppress deprecated declaration warnings in compatibility
|
||||
* function
|
||||
*/
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
|
||||
gicv2_secure_spis_configure_props(driver_data->gicd_base,
|
||||
driver_data->interrupt_props,
|
||||
driver_data->interrupt_props_num);
|
||||
|
||||
assert(driver_data->g0_interrupt_array);
|
||||
|
||||
/* Configure the G0 SPIs */
|
||||
gicv2_secure_spis_configure(driver_data->gicd_base,
|
||||
driver_data->g0_interrupt_num,
|
||||
driver_data->g0_interrupt_array);
|
||||
#pragma GCC diagnostic pop
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Re-enable the secure SPIs now that they have been configured */
|
||||
gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT);
|
||||
|
|
@ -169,35 +131,8 @@ void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data)
|
|||
assert(plat_driver_data->gicd_base != 0U);
|
||||
assert(plat_driver_data->gicc_base != 0U);
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (plat_driver_data->interrupt_props == NULL) {
|
||||
/* Interrupt properties array size must be 0 */
|
||||
assert(plat_driver_data->interrupt_props_num == 0);
|
||||
|
||||
/*
|
||||
* Suppress deprecated declaration warnings in compatibility
|
||||
* function
|
||||
*/
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
|
||||
|
||||
/*
|
||||
* If there are no interrupts of a particular type, then the
|
||||
* number of interrupts of that type should be 0 and vice-versa.
|
||||
*/
|
||||
assert(plat_driver_data->g0_interrupt_array ?
|
||||
plat_driver_data->g0_interrupt_num :
|
||||
plat_driver_data->g0_interrupt_num == 0);
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
WARN("Using deprecated integer interrupt array in "
|
||||
"gicv2_driver_data_t\n");
|
||||
WARN("Please migrate to using an interrupt_prop_t array\n");
|
||||
}
|
||||
#else
|
||||
assert(plat_driver_data->interrupt_props_num > 0 ?
|
||||
plat_driver_data->interrupt_props != NULL : 1);
|
||||
#endif
|
||||
|
||||
/* Ensure that this is a GICv2 system */
|
||||
gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
|
||||
|
|
|
|||
|
|
@ -15,14 +15,6 @@
|
|||
* Private function prototypes
|
||||
******************************************************************************/
|
||||
void gicv2_spis_configure_defaults(uintptr_t gicd_base);
|
||||
#if !ERROR_DEPRECATED
|
||||
void gicv2_secure_spis_configure(uintptr_t gicd_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list);
|
||||
void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list);
|
||||
#endif
|
||||
void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
|
||||
const interrupt_prop_t *interrupt_props,
|
||||
unsigned int interrupt_props_num);
|
||||
|
|
|
|||
|
|
@ -377,56 +377,6 @@ void gicv3_spis_config_defaults(uintptr_t gicd_base)
|
|||
gicd_write_icfgr(gicd_base, index, 0U);
|
||||
}
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
/*******************************************************************************
|
||||
* Helper function to configure secure G0 and G1S SPIs.
|
||||
******************************************************************************/
|
||||
void gicv3_secure_spis_config(uintptr_t gicd_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list,
|
||||
unsigned int int_grp)
|
||||
{
|
||||
unsigned int index, irq_num;
|
||||
unsigned long long gic_affinity_val;
|
||||
|
||||
assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
|
||||
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
|
||||
if (num_ints != 0U)
|
||||
assert(sec_intr_list != NULL);
|
||||
|
||||
for (index = 0U; index < num_ints; index++) {
|
||||
irq_num = sec_intr_list[index];
|
||||
if (irq_num >= MIN_SPI_ID) {
|
||||
|
||||
/* Configure this interrupt as a secure interrupt */
|
||||
gicd_clr_igroupr(gicd_base, irq_num);
|
||||
|
||||
/* Configure this interrupt as G0 or a G1S interrupt */
|
||||
if (int_grp == INTR_GROUP1S)
|
||||
gicd_set_igrpmodr(gicd_base, irq_num);
|
||||
else
|
||||
gicd_clr_igrpmodr(gicd_base, irq_num);
|
||||
|
||||
/* Set the priority of this interrupt */
|
||||
gicd_set_ipriorityr(gicd_base,
|
||||
irq_num,
|
||||
GIC_HIGHEST_SEC_PRIORITY);
|
||||
|
||||
/* Target SPIs to the primary CPU */
|
||||
gic_affinity_val =
|
||||
gicd_irouter_val_from_mpidr(read_mpidr(), 0U);
|
||||
gicd_write_irouter(gicd_base,
|
||||
irq_num,
|
||||
gic_affinity_val);
|
||||
|
||||
/* Enable this interrupt */
|
||||
gicd_set_isenabler(gicd_base, irq_num);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Helper function to configure properties of secure SPIs
|
||||
******************************************************************************/
|
||||
|
|
@ -512,47 +462,6 @@ void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
|
|||
gicr_write_icfgr1(gicr_base, 0U);
|
||||
}
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
/*******************************************************************************
|
||||
* Helper function to configure secure G0 and G1S SPIs.
|
||||
******************************************************************************/
|
||||
void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list,
|
||||
unsigned int int_grp)
|
||||
{
|
||||
unsigned int index, irq_num;
|
||||
|
||||
assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
|
||||
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
|
||||
if (num_ints != 0U)
|
||||
assert(sec_intr_list != NULL);
|
||||
|
||||
for (index = 0; index < num_ints; index++) {
|
||||
irq_num = sec_intr_list[index];
|
||||
if (irq_num < MIN_SPI_ID) {
|
||||
|
||||
/* Configure this interrupt as a secure interrupt */
|
||||
gicr_clr_igroupr0(gicr_base, irq_num);
|
||||
|
||||
/* Configure this interrupt as G0 or a G1S interrupt */
|
||||
if (int_grp == INTR_GROUP1S)
|
||||
gicr_set_igrpmodr0(gicr_base, irq_num);
|
||||
else
|
||||
gicr_clr_igrpmodr0(gicr_base, irq_num);
|
||||
|
||||
/* Set the priority of this interrupt */
|
||||
gicr_set_ipriorityr(gicr_base,
|
||||
irq_num,
|
||||
GIC_HIGHEST_SEC_PRIORITY);
|
||||
|
||||
/* Enable this interrupt */
|
||||
gicr_set_isenabler0(gicr_base, irq_num);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
|
||||
******************************************************************************/
|
||||
|
|
|
|||
|
|
@ -67,45 +67,8 @@ void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
|
|||
|
||||
assert(IS_IN_EL3());
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (plat_driver_data->interrupt_props == NULL) {
|
||||
/* Interrupt properties array size must be 0 */
|
||||
assert(plat_driver_data->interrupt_props_num == 0);
|
||||
|
||||
/*
|
||||
* Suppress deprecated declaration warnings in compatibility
|
||||
* function
|
||||
*/
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
|
||||
|
||||
/*
|
||||
* The platform should provide a list of at least one type of
|
||||
* interrupt.
|
||||
*/
|
||||
assert(plat_driver_data->g0_interrupt_array ||
|
||||
plat_driver_data->g1s_interrupt_array);
|
||||
|
||||
/*
|
||||
* If there are no interrupts of a particular type, then the
|
||||
* number of interrupts of that type should be 0 and vice-versa.
|
||||
*/
|
||||
assert(plat_driver_data->g0_interrupt_array ?
|
||||
plat_driver_data->g0_interrupt_num :
|
||||
plat_driver_data->g0_interrupt_num == 0);
|
||||
assert(plat_driver_data->g1s_interrupt_array ?
|
||||
plat_driver_data->g1s_interrupt_num :
|
||||
plat_driver_data->g1s_interrupt_num == 0);
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
WARN("Using deprecated integer interrupt arrays in "
|
||||
"gicv3_driver_data_t\n");
|
||||
WARN("Please migrate to using interrupt_prop_t arrays\n");
|
||||
}
|
||||
#else
|
||||
assert(plat_driver_data->interrupt_props_num > 0 ?
|
||||
plat_driver_data->interrupt_props != NULL : 1);
|
||||
#endif
|
||||
|
||||
/* Check for system register support */
|
||||
#ifdef AARCH32
|
||||
|
|
@ -193,45 +156,10 @@ void gicv3_distif_init(void)
|
|||
/* Set the default attribute of all SPIs */
|
||||
gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (gicv3_driver_data->interrupt_props != NULL) {
|
||||
#endif
|
||||
bitmap = gicv3_secure_spis_config_props(
|
||||
gicv3_driver_data->gicd_base,
|
||||
gicv3_driver_data->interrupt_props,
|
||||
gicv3_driver_data->interrupt_props_num);
|
||||
#if !ERROR_DEPRECATED
|
||||
} else {
|
||||
/*
|
||||
* Suppress deprecated declaration warnings in compatibility
|
||||
* function
|
||||
*/
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
|
||||
|
||||
assert(gicv3_driver_data->g1s_interrupt_array ||
|
||||
gicv3_driver_data->g0_interrupt_array);
|
||||
|
||||
/* Configure the G1S SPIs */
|
||||
if (gicv3_driver_data->g1s_interrupt_array) {
|
||||
gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
|
||||
gicv3_driver_data->g1s_interrupt_num,
|
||||
gicv3_driver_data->g1s_interrupt_array,
|
||||
INTR_GROUP1S);
|
||||
bitmap |= CTLR_ENABLE_G1S_BIT;
|
||||
}
|
||||
|
||||
/* Configure the G0 SPIs */
|
||||
if (gicv3_driver_data->g0_interrupt_array) {
|
||||
gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
|
||||
gicv3_driver_data->g0_interrupt_num,
|
||||
gicv3_driver_data->g0_interrupt_array,
|
||||
INTR_GROUP0);
|
||||
bitmap |= CTLR_ENABLE_G0_BIT;
|
||||
}
|
||||
#pragma GCC diagnostic pop
|
||||
}
|
||||
#endif
|
||||
bitmap = gicv3_secure_spis_config_props(
|
||||
gicv3_driver_data->gicd_base,
|
||||
gicv3_driver_data->interrupt_props,
|
||||
gicv3_driver_data->interrupt_props_num);
|
||||
|
||||
/* Enable the secure SPIs now that they have been configured */
|
||||
gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE);
|
||||
|
|
@ -266,44 +194,9 @@ void gicv3_rdistif_init(unsigned int proc_num)
|
|||
/* Set the default attribute of all SGIs and PPIs */
|
||||
gicv3_ppi_sgi_config_defaults(gicr_base);
|
||||
|
||||
#if !ERROR_DEPRECATED
|
||||
if (gicv3_driver_data->interrupt_props != NULL) {
|
||||
#endif
|
||||
bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
|
||||
gicv3_driver_data->interrupt_props,
|
||||
gicv3_driver_data->interrupt_props_num);
|
||||
#if !ERROR_DEPRECATED
|
||||
} else {
|
||||
/*
|
||||
* Suppress deprecated declaration warnings in compatibility
|
||||
* function
|
||||
*/
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
|
||||
|
||||
assert(gicv3_driver_data->g1s_interrupt_array ||
|
||||
gicv3_driver_data->g0_interrupt_array);
|
||||
|
||||
/* Configure the G1S SGIs/PPIs */
|
||||
if (gicv3_driver_data->g1s_interrupt_array) {
|
||||
gicv3_secure_ppi_sgi_config(gicr_base,
|
||||
gicv3_driver_data->g1s_interrupt_num,
|
||||
gicv3_driver_data->g1s_interrupt_array,
|
||||
INTR_GROUP1S);
|
||||
bitmap |= CTLR_ENABLE_G1S_BIT;
|
||||
}
|
||||
|
||||
/* Configure the G0 SGIs/PPIs */
|
||||
if (gicv3_driver_data->g0_interrupt_array) {
|
||||
gicv3_secure_ppi_sgi_config(gicr_base,
|
||||
gicv3_driver_data->g0_interrupt_num,
|
||||
gicv3_driver_data->g0_interrupt_array,
|
||||
INTR_GROUP0);
|
||||
bitmap |= CTLR_ENABLE_G0_BIT;
|
||||
}
|
||||
#pragma GCC diagnostic pop
|
||||
}
|
||||
#endif
|
||||
bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
|
||||
gicv3_driver_data->interrupt_props,
|
||||
gicv3_driver_data->interrupt_props_num);
|
||||
|
||||
/* Enable interrupt groups as required, if not already */
|
||||
if ((ctlr & bitmap) != bitmap)
|
||||
|
|
|
|||
|
|
@ -95,16 +95,6 @@ void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg);
|
|||
******************************************************************************/
|
||||
void gicv3_spis_config_defaults(uintptr_t gicd_base);
|
||||
void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
|
||||
#if !ERROR_DEPRECATED
|
||||
void gicv3_secure_spis_config(uintptr_t gicd_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list,
|
||||
unsigned int int_grp);
|
||||
void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
|
||||
unsigned int num_ints,
|
||||
const unsigned int *sec_intr_list,
|
||||
unsigned int int_grp);
|
||||
#endif
|
||||
unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
|
||||
const interrupt_prop_t *interrupt_props,
|
||||
unsigned int interrupt_props_num);
|
||||
|
|
|
|||
|
|
@ -1,34 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __ARM_GIC_H__
|
||||
#define __ARM_GIC_H__
|
||||
|
||||
#include <cdefs.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Function declarations
|
||||
******************************************************************************/
|
||||
void arm_gic_init(uintptr_t gicc_base,
|
||||
uintptr_t gicd_base,
|
||||
uintptr_t gicr_base,
|
||||
const unsigned int *irq_sec_ptr,
|
||||
unsigned int num_irqs) __deprecated;
|
||||
void arm_gic_setup(void) __deprecated;
|
||||
void arm_gic_cpuif_deactivate(void) __deprecated;
|
||||
void arm_gic_cpuif_setup(void) __deprecated;
|
||||
void arm_gic_pcpu_distif_setup(void) __deprecated;
|
||||
|
||||
uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
|
||||
uint32_t security_state) __deprecated;
|
||||
uint32_t arm_gic_get_pending_interrupt_type(void) __deprecated;
|
||||
uint32_t arm_gic_get_pending_interrupt_id(void) __deprecated;
|
||||
uint32_t arm_gic_acknowledge_interrupt(void) __deprecated;
|
||||
void arm_gic_end_of_interrupt(uint32_t id) __deprecated;
|
||||
uint32_t arm_gic_get_interrupt_type(uint32_t id) __deprecated;
|
||||
|
||||
#endif /* __GIC_H__ */
|
||||
|
|
@ -1,280 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __GIC_V2_H__
|
||||
#define __GIC_V2_H__
|
||||
|
||||
/* The macros required here are additional to those in gic_common.h. */
|
||||
#include <gic_common.h>
|
||||
|
||||
/******************************************************************************
|
||||
* THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
|
||||
* and for GICv3 systems, use the driver in gicv3.h.
|
||||
*****************************************************************************/
|
||||
#if ERROR_DEPRECATED
|
||||
#error " The legacy ARM GIC driver is deprecated."
|
||||
#endif
|
||||
|
||||
#define GIC400_NUM_SPIS U(480)
|
||||
#define MAX_PPIS U(14)
|
||||
#define MAX_SGIS U(16)
|
||||
|
||||
|
||||
#define GRP0 U(0)
|
||||
#define GRP1 U(1)
|
||||
#define GIC_TARGET_CPU_MASK U(0xff)
|
||||
|
||||
#define ENABLE_GRP0 (U(1) << 0)
|
||||
#define ENABLE_GRP1 (U(1) << 1)
|
||||
|
||||
/* Distributor interface definitions */
|
||||
#define GICD_ITARGETSR U(0x800)
|
||||
#define GICD_SGIR U(0xF00)
|
||||
#define GICD_CPENDSGIR U(0xF10)
|
||||
#define GICD_SPENDSGIR U(0xF20)
|
||||
|
||||
#define CPENDSGIR_SHIFT U(2)
|
||||
#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
|
||||
|
||||
/* GICD_TYPER bit definitions */
|
||||
#define IT_LINES_NO_MASK U(0x1f)
|
||||
|
||||
/* Physical CPU Interface registers */
|
||||
#define GICC_CTLR U(0x0)
|
||||
#define GICC_PMR U(0x4)
|
||||
#define GICC_BPR U(0x8)
|
||||
#define GICC_IAR U(0xC)
|
||||
#define GICC_EOIR U(0x10)
|
||||
#define GICC_RPR U(0x14)
|
||||
#define GICC_HPPIR U(0x18)
|
||||
#define GICC_AHPPIR U(0x28)
|
||||
#define GICC_IIDR U(0xFC)
|
||||
#define GICC_DIR U(0x1000)
|
||||
#define GICC_PRIODROP GICC_EOIR
|
||||
|
||||
/* Common CPU Interface definitions */
|
||||
#define INT_ID_MASK U(0x3ff)
|
||||
|
||||
/* GICC_CTLR bit definitions */
|
||||
#define EOI_MODE_NS (U(1) << 10)
|
||||
#define EOI_MODE_S (U(1) << 9)
|
||||
#define IRQ_BYP_DIS_GRP1 (U(1) << 8)
|
||||
#define FIQ_BYP_DIS_GRP1 (U(1) << 7)
|
||||
#define IRQ_BYP_DIS_GRP0 (U(1) << 6)
|
||||
#define FIQ_BYP_DIS_GRP0 (U(1) << 5)
|
||||
#define CBPR (U(1) << 4)
|
||||
#define FIQ_EN (U(1) << 3)
|
||||
#define ACK_CTL (U(1) << 2)
|
||||
|
||||
/* GICC_IIDR bit masks and shifts */
|
||||
#define GICC_IIDR_PID_SHIFT U(20)
|
||||
#define GICC_IIDR_ARCH_SHIFT U(16)
|
||||
#define GICC_IIDR_REV_SHIFT U(12)
|
||||
#define GICC_IIDR_IMP_SHIFT U(0)
|
||||
|
||||
#define GICC_IIDR_PID_MASK U(0xfff)
|
||||
#define GICC_IIDR_ARCH_MASK U(0xf)
|
||||
#define GICC_IIDR_REV_MASK U(0xf)
|
||||
#define GICC_IIDR_IMP_MASK U(0xfff)
|
||||
|
||||
/* HYP view virtual CPU Interface registers */
|
||||
#define GICH_CTL U(0x0)
|
||||
#define GICH_VTR U(0x4)
|
||||
#define GICH_ELRSR0 U(0x30)
|
||||
#define GICH_ELRSR1 U(0x34)
|
||||
#define GICH_APR0 U(0xF0)
|
||||
#define GICH_LR_BASE U(0x100)
|
||||
|
||||
/* Virtual CPU Interface registers */
|
||||
#define GICV_CTL U(0x0)
|
||||
#define GICV_PRIMASK U(0x4)
|
||||
#define GICV_BP U(0x8)
|
||||
#define GICV_INTACK U(0xC)
|
||||
#define GICV_EOI U(0x10)
|
||||
#define GICV_RUNNINGPRI U(0x14)
|
||||
#define GICV_HIGHESTPEND U(0x18)
|
||||
#define GICV_DEACTIVATE U(0x1000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <mmio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC Distributor function prototypes
|
||||
******************************************************************************/
|
||||
|
||||
unsigned int gicd_read_igroupr(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_isenabler(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_icenabler(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_ispendr(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_icpendr(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_isactiver(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_icactiver(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_itargetsr(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_icfgr(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int);
|
||||
unsigned int gicd_read_spendsgir(uintptr_t, unsigned int);
|
||||
void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int);
|
||||
unsigned int gicd_get_igroupr(uintptr_t, unsigned int);
|
||||
void gicd_set_igroupr(uintptr_t, unsigned int);
|
||||
void gicd_clr_igroupr(uintptr_t, unsigned int);
|
||||
void gicd_set_isenabler(uintptr_t, unsigned int);
|
||||
void gicd_set_icenabler(uintptr_t, unsigned int);
|
||||
void gicd_set_ispendr(uintptr_t, unsigned int);
|
||||
void gicd_set_icpendr(uintptr_t, unsigned int);
|
||||
void gicd_set_isactiver(uintptr_t, unsigned int);
|
||||
void gicd_set_icactiver(uintptr_t, unsigned int);
|
||||
void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int);
|
||||
void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int);
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC Distributor interface accessors for reading entire registers
|
||||
******************************************************************************/
|
||||
|
||||
static inline unsigned int gicd_read_ctlr(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICD_CTLR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicd_read_typer(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICD_TYPER);
|
||||
}
|
||||
|
||||
static inline unsigned int gicd_read_sgir(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICD_SGIR);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC Distributor interface accessors for writing entire registers
|
||||
******************************************************************************/
|
||||
|
||||
static inline void gicd_write_ctlr(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICD_CTLR, val);
|
||||
}
|
||||
|
||||
static inline void gicd_write_sgir(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICD_SGIR, val);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC CPU interface accessors for reading entire registers
|
||||
******************************************************************************/
|
||||
|
||||
static inline unsigned int gicc_read_ctlr(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_CTLR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_pmr(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_PMR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_BPR(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_BPR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_IAR(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_IAR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_EOIR(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_EOIR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_hppir(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_HPPIR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_ahppir(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_AHPPIR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_dir(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_DIR);
|
||||
}
|
||||
|
||||
static inline unsigned int gicc_read_iidr(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICC_IIDR);
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC CPU interface accessors for writing entire registers
|
||||
******************************************************************************/
|
||||
|
||||
static inline void gicc_write_ctlr(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICC_CTLR, val);
|
||||
}
|
||||
|
||||
static inline void gicc_write_pmr(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICC_PMR, val);
|
||||
}
|
||||
|
||||
static inline void gicc_write_BPR(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICC_BPR, val);
|
||||
}
|
||||
|
||||
|
||||
static inline void gicc_write_IAR(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICC_IAR, val);
|
||||
}
|
||||
|
||||
static inline void gicc_write_EOIR(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICC_EOIR, val);
|
||||
}
|
||||
|
||||
static inline void gicc_write_hppir(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICC_HPPIR, val);
|
||||
}
|
||||
|
||||
static inline void gicc_write_dir(uintptr_t base, unsigned int val)
|
||||
{
|
||||
mmio_write_32(base + GICC_DIR, val);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototype of function to map an interrupt type to the interrupt line used to
|
||||
* signal it.
|
||||
******************************************************************************/
|
||||
uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
|
||||
|
||||
#endif /*__ASSEMBLY__*/
|
||||
|
||||
#endif /* __GIC_V2_H__ */
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __GIC_V3_H__
|
||||
#define __GIC_V3_H__
|
||||
|
||||
/******************************************************************************
|
||||
* THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h
|
||||
* and for GICv3 systems, use the driver in gicv3.h.
|
||||
*****************************************************************************/
|
||||
#if ERROR_DEPRECATED
|
||||
#error " The legacy ARM GIC driver is deprecated."
|
||||
#endif
|
||||
|
||||
#include <mmio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* GICv3 Re-distributor interface registers & shifts */
|
||||
#define GICR_PCPUBASE_SHIFT 0x11
|
||||
#define GICR_TYPER 0x08
|
||||
#define GICR_WAKER 0x14
|
||||
|
||||
/* GICR_WAKER bit definitions */
|
||||
#define WAKER_CA (U(1) << 2)
|
||||
#define WAKER_PS (U(1) << 1)
|
||||
|
||||
/* GICR_TYPER bit definitions */
|
||||
#define GICR_TYPER_AFF_SHIFT 32
|
||||
#define GICR_TYPER_AFF_MASK 0xffffffff
|
||||
#define GICR_TYPER_LAST (U(1) << 4)
|
||||
|
||||
/* GICv3 ICC_SRE register bit definitions*/
|
||||
#define ICC_SRE_EN (U(1) << 3)
|
||||
#define ICC_SRE_SRE (U(1) << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* GICv3 defintions
|
||||
******************************************************************************/
|
||||
#define GICV3_AFFLVL_MASK 0xff
|
||||
#define GICV3_AFF0_SHIFT 0
|
||||
#define GICV3_AFF1_SHIFT 8
|
||||
#define GICV3_AFF2_SHIFT 16
|
||||
#define GICV3_AFF3_SHIFT 24
|
||||
#define GICV3_AFFINITY_MASK 0xffffffff
|
||||
|
||||
/*******************************************************************************
|
||||
* Function prototypes
|
||||
******************************************************************************/
|
||||
uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr);
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC Redistributor interface accessors
|
||||
******************************************************************************/
|
||||
static inline uint32_t gicr_read_waker(uintptr_t base)
|
||||
{
|
||||
return mmio_read_32(base + GICR_WAKER);
|
||||
}
|
||||
|
||||
static inline void gicr_write_waker(uintptr_t base, uint32_t val)
|
||||
{
|
||||
mmio_write_32(base + GICR_WAKER, val);
|
||||
}
|
||||
|
||||
static inline uint64_t gicr_read_typer(uintptr_t base)
|
||||
{
|
||||
return mmio_read_64(base + GICR_TYPER);
|
||||
}
|
||||
|
||||
|
||||
#endif /* __GIC_V3_H__ */
|
||||
|
|
@ -7,6 +7,8 @@
|
|||
#ifndef __GICV2_H__
|
||||
#define __GICV2_H__
|
||||
|
||||
#include <gic_common.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* GICv2 miscellaneous definitions
|
||||
******************************************************************************/
|
||||
|
|
@ -132,14 +134,6 @@
|
|||
* The 'gicc_base' field contains the base address of the CPU Interface
|
||||
* programmer's view.
|
||||
*
|
||||
* The 'g0_interrupt_array' field is a pointer to an array in which each entry
|
||||
* corresponds to an ID of a Group 0 interrupt. This field is ignored when
|
||||
* 'interrupt_props' field is used. This field is deprecated.
|
||||
*
|
||||
* The 'g0_interrupt_num' field contains the number of entries in the
|
||||
* 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
|
||||
* used. This field is deprecated.
|
||||
*
|
||||
* The 'target_masks' is a pointer to an array containing 'target_masks_num'
|
||||
* elements. The GIC driver will populate the array with per-PE target mask to
|
||||
* use to when targeting interrupts.
|
||||
|
|
@ -155,10 +149,6 @@
|
|||
typedef struct gicv2_driver_data {
|
||||
uintptr_t gicd_base;
|
||||
uintptr_t gicc_base;
|
||||
#if !ERROR_DEPRECATED
|
||||
unsigned int g0_interrupt_num __deprecated;
|
||||
const unsigned int *g0_interrupt_array __deprecated;
|
||||
#endif
|
||||
unsigned int *target_masks;
|
||||
unsigned int target_masks_num;
|
||||
const interrupt_prop_t *interrupt_props;
|
||||
|
|
|
|||
|
|
@ -276,23 +276,6 @@ static inline void gicv3_end_of_interrupt(unsigned int id)
|
|||
* The 'gicr_base' field contains the base address of the Re-distributor
|
||||
* interface programmer's view.
|
||||
*
|
||||
* The 'g0_interrupt_array' field is a pointer to an array in which each entry
|
||||
* corresponds to an ID of a Group 0 interrupt. This field is ignored when
|
||||
* 'interrupt_props' field is used. This field is deprecated.
|
||||
*
|
||||
* The 'g0_interrupt_num' field contains the number of entries in the
|
||||
* 'g0_interrupt_array'. This field is ignored when 'interrupt_props' field is
|
||||
* used. This field is deprecated.
|
||||
*
|
||||
* The 'g1s_interrupt_array' field is a pointer to an array in which each entry
|
||||
* corresponds to an ID of a Group 1 interrupt. This field is ignored when
|
||||
* 'interrupt_props' field is used. This field is deprecated.
|
||||
*
|
||||
* The 'g1s_interrupt_num' field contains the number of entries in the
|
||||
* 'g1s_interrupt_array'. This field must be 0 if 'interrupt_props' field is
|
||||
* used. This field is ignored when 'interrupt_props' field is used. This field
|
||||
* is deprecated.
|
||||
*
|
||||
* The 'interrupt_props' field is a pointer to an array that enumerates secure
|
||||
* interrupts and their properties. If this field is not NULL, both
|
||||
* 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
|
||||
|
|
@ -326,12 +309,6 @@ typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
|
|||
typedef struct gicv3_driver_data {
|
||||
uintptr_t gicd_base;
|
||||
uintptr_t gicr_base;
|
||||
#if !ERROR_DEPRECATED
|
||||
unsigned int g0_interrupt_num __deprecated;
|
||||
unsigned int g1s_interrupt_num __deprecated;
|
||||
const unsigned int *g0_interrupt_array __deprecated;
|
||||
const unsigned int *g1s_interrupt_array __deprecated;
|
||||
#endif
|
||||
const interrupt_prop_t *interrupt_props;
|
||||
unsigned int interrupt_props_num;
|
||||
unsigned int rdistif_num;
|
||||
|
|
|
|||
|
|
@ -23,10 +23,6 @@ ARCH := aarch64
|
|||
ARM_ARCH_MAJOR := 8
|
||||
ARM_ARCH_MINOR := 0
|
||||
|
||||
# Determine the version of ARM GIC architecture to use for interrupt management
|
||||
# in EL3. The platform port can change this value if needed.
|
||||
ARM_GIC_ARCH := 2
|
||||
|
||||
# Base commit to perform code check on
|
||||
BASE_COMMIT := origin/master
|
||||
|
||||
|
|
|
|||
|
|
@ -1,49 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
#include <arm_gic.h>
|
||||
|
||||
/*
|
||||
* The following platform GIC functions are weakly defined. They
|
||||
* provide typical implementations that may be re-used by multiple
|
||||
* platforms but may also be overridden by a platform if required.
|
||||
*/
|
||||
#pragma weak plat_ic_get_pending_interrupt_id
|
||||
#pragma weak plat_ic_get_pending_interrupt_type
|
||||
#pragma weak plat_ic_acknowledge_interrupt
|
||||
#pragma weak plat_ic_get_interrupt_type
|
||||
#pragma weak plat_ic_end_of_interrupt
|
||||
#pragma weak plat_interrupt_type_to_line
|
||||
|
||||
uint32_t plat_ic_get_pending_interrupt_id(void)
|
||||
{
|
||||
return arm_gic_get_pending_interrupt_id();
|
||||
}
|
||||
|
||||
uint32_t plat_ic_get_pending_interrupt_type(void)
|
||||
{
|
||||
return arm_gic_get_pending_interrupt_type();
|
||||
}
|
||||
|
||||
uint32_t plat_ic_acknowledge_interrupt(void)
|
||||
{
|
||||
return arm_gic_acknowledge_interrupt();
|
||||
}
|
||||
|
||||
uint32_t plat_ic_get_interrupt_type(uint32_t id)
|
||||
{
|
||||
return arm_gic_get_interrupt_type(id);
|
||||
}
|
||||
|
||||
void plat_ic_end_of_interrupt(uint32_t id)
|
||||
{
|
||||
arm_gic_end_of_interrupt(id);
|
||||
}
|
||||
|
||||
uint32_t plat_interrupt_type_to_line(uint32_t type,
|
||||
uint32_t security_state)
|
||||
{
|
||||
return arm_gic_interrupt_type_to_line(type, security_state);
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue