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https://github.com/ARM-software/arm-trusted-firmware.git
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57d1e5faf2
Commit 4c0d039076 ("Rework type usage in Trusted Firmware") changed
the type usage in struct declarations, but did not touch the definition
side. Fix the type mismatch.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <debug.h>
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#include <gic_v3.h>
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uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr)
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{
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uint32_t cpu_aff, gicr_aff;
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uint64_t gicr_typer;
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uintptr_t addr;
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/* Construct the affinity as used by GICv3. MPIDR and GIC affinity level
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* mask is the same.
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*/
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cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) <<
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GICV3_AFF0_SHIFT;
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cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) <<
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GICV3_AFF1_SHIFT;
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cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) <<
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GICV3_AFF2_SHIFT;
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cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) <<
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GICV3_AFF3_SHIFT;
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addr = gicr_base;
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do {
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gicr_typer = gicr_read_typer(addr);
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gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) &
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GICR_TYPER_AFF_MASK;
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if (cpu_aff == gicr_aff) {
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/* Disable this print for now as it appears every time
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* when using PSCI CPU_SUSPEND.
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* TODO: Print this only the first time for each CPU.
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* INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at %p\n",
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* mpidr, (void *) addr);
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*/
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return addr;
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}
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/* TODO:
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* For GICv4 we need to adjust the Base address based on
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* GICR_TYPER.VLPIS
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*/
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addr += (1 << GICR_PCPUBASE_SHIFT);
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} while (!(gicr_typer & GICR_TYPER_LAST));
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/* If we get here we did not find a match. */
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ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr);
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return (uintptr_t)NULL;
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}
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