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Merge "refactor(ast2700): adopt RESET_TO_BL31 boot flow" into integration

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This commit is contained in:
Manish V Badarkhe 2023-09-29 08:56:50 +02:00 • committed by TrustedFirmware Code Review
commit f80323da12
5 changed files with 41 additions and 10 deletions
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4
docs/plat/ast2700.rst
View file

@ -7,11 +7,11 @@ Each core operates at 1.6GHz.
Boot Flow Boot Flow
--------- ---------
BootRom --> BL1/BL2 --> TF-A BL31 --> BL32 (optional) --> BL33 --> Linux Kernel BootRom --> TF-A BL31 --> BL32 --> BL33 --> Linux Kernel
How to build How to build
------------ ------------
.. code:: shell .. code:: shell
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700 make CROSS_COMPILE=aarch64-linux-gnu- PLAT=ast2700 SPD=opteed

3
plat/aspeed/ast2700/include/platform_reg.h
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@ -19,10 +19,9 @@
/* CPU-die SCU */ /* CPU-die SCU */
#define SCU_CPU_BASE U(0x12c02000) #define SCU_CPU_BASE U(0x12c02000)
#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780) #define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780)
#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) #define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788)
#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) #define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790)
#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) #define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798)
#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0)
#endif /* PLATFORM_REG_H */ #endif /* PLATFORM_REG_H */

10
plat/aspeed/ast2700/plat_bl31_setup.c
View file

@ -10,6 +10,7 @@
#include <drivers/arm/gicv3.h> #include <drivers/arm/gicv3.h>
#include <drivers/console.h> #include <drivers/console.h>
#include <drivers/ti/uart/uart_16550.h> #include <drivers/ti/uart/uart_16550.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h> #include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
#include <platform_def.h> #include <platform_def.h>
@ -55,7 +56,14 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH); console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info); SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_2, 0);
bl32_ep_info.pc = BL32_BASE;
SET_SECURITY_STATE(bl32_ep_info.h.attr, SECURE);
SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_2, 0);
bl33_ep_info.pc = mmio_read_64(SCU_CPU_SMP_EP0);
bl33_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
SET_SECURITY_STATE(bl33_ep_info.h.attr, NON_SECURE);
} }
void bl31_plat_arch_setup(void) void bl31_plat_arch_setup(void)

22
plat/aspeed/ast2700/plat_helpers.S
View file

@ -10,6 +10,7 @@
#include <cortex_a35.h> #include <cortex_a35.h>
#include <platform_def.h> #include <platform_def.h>
.globl platform_mem_init
.globl plat_is_my_cpu_primary .globl plat_is_my_cpu_primary
.globl plat_my_core_pos .globl plat_my_core_pos
.globl plat_secondary_cold_boot_setup .globl plat_secondary_cold_boot_setup
@ -18,6 +19,12 @@
.globl plat_crash_console_putc .globl plat_crash_console_putc
.globl plat_crash_console_flush .globl plat_crash_console_flush
/* void platform_mem_init(void); */
func platform_mem_init
/* DRAM init. is done by preceding MCU */
ret
endfunc platform_mem_init
/* unsigned int plat_is_my_cpu_primary(void); */ /* unsigned int plat_is_my_cpu_primary(void); */
func plat_is_my_cpu_primary func plat_is_my_cpu_primary
mrs x0, mpidr_el1 mrs x0, mpidr_el1
@ -37,6 +44,21 @@ func plat_my_core_pos
ret ret
endfunc plat_my_core_pos endfunc plat_my_core_pos
/* void plat_secondary_cold_boot_setup (void); */
func plat_secondary_cold_boot_setup
mov x0, xzr
bl plat_my_core_pos
mov_imm x1, SCU_CPU_SMP_EP0
add x1, x1, x0, lsl #3
poll_smp_mbox_go:
wfe
ldr x0, [x1]
cmp x0, xzr
beq poll_smp_mbox_go
br x0
endfunc plat_secondary_cold_boot_setup
/* unsigned int plat_get_syscnt_freq2(void); */ /* unsigned int plat_get_syscnt_freq2(void); */
func plat_get_syscnt_freq2 func plat_get_syscnt_freq2
mov_imm w0, PLAT_SYSCNT_CLKIN_HZ mov_imm w0, PLAT_SYSCNT_CLKIN_HZ

4
plat/aspeed/ast2700/platform.mk
View file

@ -25,8 +25,10 @@ BL31_SOURCES += \
${GICV3_SOURCES} \ ${GICV3_SOURCES} \
${XLAT_TABLES_LIB_SRCS} ${XLAT_TABLES_LIB_SRCS}
RESET_TO_BL31 := 1
PROGRAMMABLE_RESET_ADDRESS := 1 PROGRAMMABLE_RESET_ADDRESS := 1
COLD_BOOT_SINGLE_CPU := 1 COLD_BOOT_SINGLE_CPU := 0
ENABLE_SVE_FOR_NS := 0 ENABLE_SVE_FOR_NS := 0