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https://github.com/ARM-software/arm-trusted-firmware.git
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564e073cd5
Revise the AST2700 boot flow to the RESET_TO_BL31 scheme. The execution of BL1/2 can be saved from ARM CA35 while most low level platform initialization are moved to a preceding MCU. This patch updates the build configuration and also adds the SMP mailbox setup code to hold secondary cores until they are being waken up. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Change-Id: I7e0aa6416b92b97036153db1d9a26baaa41b7b18
108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
/*
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* Copyright (c) 2023, Aspeed Technology Inc.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/console.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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static console_t console;
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static entry_point_info_t bl32_ep_info;
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static entry_point_info_t bl33_ep_info;
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static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static unsigned int plat_mpidr_to_core_pos(u_register_t mpidr)
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{
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/* to workaround the return type mismatch */
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return plat_core_pos_by_mpidr(mpidr);
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}
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static const gicv3_driver_data_t plat_gic_data = {
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.gicd_base = GICD_BASE,
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.gicr_base = GICR_BASE,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = plat_mpidr_to_core_pos,
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};
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static const mmap_region_t plat_mmap[] = {
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MAP_REGION_FLAT(GICD_BASE, GICD_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(GICR_BASE, GICR_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(UART_BASE, PAGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(SCU_CPU_BASE, PAGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE),
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{ 0 }
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};
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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console_16550_register(CONSOLE_UART_BASE, CONSOLE_UART_CLKIN_HZ,
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CONSOLE_UART_BAUDRATE, &console);
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console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
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SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_2, 0);
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bl32_ep_info.pc = BL32_BASE;
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SET_SECURITY_STATE(bl32_ep_info.h.attr, SECURE);
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SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_2, 0);
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bl33_ep_info.pc = mmio_read_64(SCU_CPU_SMP_EP0);
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bl33_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl33_ep_info.h.attr, NON_SECURE);
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}
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void bl31_plat_arch_setup(void)
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{
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mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
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BL_CODE_END - BL_CODE_BASE,
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MT_CODE | MT_SECURE);
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mmap_add_region(BL_CODE_END, BL_CODE_END,
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BL_END - BL_CODE_END,
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MT_RW_DATA | MT_SECURE);
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mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE,
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MT_MEMORY | MT_RW);
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mmap_add(plat_mmap);
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init_xlat_tables();
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enable_mmu_el3(0);
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}
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void bl31_platform_setup(void)
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{
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gicv3_driver_init(&plat_gic_data);
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *ep_info;
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ep_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
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if (!ep_info->pc) {
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return NULL;
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}
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return ep_info;
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}
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