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Merge "feat(intel): increase bl2 size limit" into integration

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This commit is contained in:
Manish Pandey 2023-11-27 16:38:45 +01:00 • committed by TrustedFirmware Code Review
commit f4bb899810
3 changed files with 3 additions and 3 deletions
plat/intel/soc
agilex/include
socfpga_plat_def.h
agilex5/include
socfpga_plat_def.h
stratix10/include
socfpga_plat_def.h

2
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -65,7 +65,7 @@
#define DEVICE4_SIZE (0x0100000000)
#define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe1b000)
#define BL2_LIMIT (0xffe2b000)
#define BL31_BASE (0x1000)
#define BL31_LIMIT (0x81000)

2
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -86,7 +86,7 @@
#define GIC_SIZE (0x00100000)
#define BL2_BASE (0x00000000)
#define BL2_LIMIT (0x0001b000)
#define BL2_LIMIT (0x0002b000)
#define BL31_BASE (0x80000000)
#define BL31_LIMIT (0x82000000)

2
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -64,7 +64,7 @@
#define DEVICE4_SIZE (0x0100000000)
#define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe1b000)
#define BL2_LIMIT (0xffe2b000)
#define BL31_BASE (0x1000)
#define BL31_LIMIT (0x81000)